Wi-Fi Module Series
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4.5. JTAG Interface
The module provides a JTAG interface for module debugging and testing. Its circuit will only be reset by
JTAG_TRST pin. Ensure the pin 35 (JTAG_TRST) is pulled down to GND with a 10 kΩ resistor during
power-up. The JTAG interface supports:
⚫ Custom internal test logic enabling (scan mode, MBIST mode).
⚫ RISC-V debug logic for CPU and system debug.
⚫ Custom JTAG block registers.
The data rate of JTAG interface will be constrained to 50 MHz in mission/functional and scan modes.
4.6. RF Antenna Interface
Appropriate antenna type and design should be used with matched antenna parameters according to
specific application. It is required to perform a comprehensive functional test for the RF design before
mass production of terminal products. The entire content of this chapter is provided for illustration only.
Analysis, evaluation and determination are still necessary when designing target products.
The module supports one antenna interface (ANT_WIFI). The impedance of antenna port is 50 Ω.
Table 8: Antenna Design Requirements
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