Quectel RM502Q-AE - Page 24

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 24 / 83
32
USIM_CLK
DO
(U)SIM clock
1.8/3.0 V power domain
33
GND
Ground
34
USIM_DATA
IO
(U)SIM card data
1.8/3.0 V power domain
35
USB_SS_RX_M
AI
USB 3.1 super-speed
receive (-)
36
USIM_VDD
PO
(U)SIM card power supply
1.8/3.0 V power domain
37
USB_SS_RX_P
AI
USB 3.1 super-speed
receive (+)
38
SDX2AP_STATUS
DO
Status indication to AP
1.8 V power domain
39
GND
Ground
40
NC
NC
41
PCIE_TX_M
AO
PCIe transmit (-)
42
NC
NC
43
PCIE_TX_P
AO
PCIe transmit (+)
44
NC
NC
45
GND
Ground
46
NC
NC
47
PCIE_RX_M
AI
PCIe receive (-)
48
NC
NC
49
PCIE_RX_P
AI
PCIe receive (+)
50
PCIE_RST_N
DI
PCIe reset.
Open drain
Active LOW.
51
GND
Ground
52
PCIE_CLKREQ_N
DO
PCIe clock request.
Open drain
Active LOW.
53
PCIE_REFCLK_M
AI,
AO
PCIe reference clock (-)
54
PCIE_WAKE_N
DO
PCIe wake up
Open drain
Active LOW
55
PCIE_REFCLK_P
AI,
AO
PCIe reference clock (+)