Quectel RM502Q-AE - Page 33

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 33 / 83
Host Module
RESET_N
Reset
Logic
GPIO
67
VDD 1.5 V
Reset pulse
200-700 ms
R1
100k
R5
100k
R4
10R
Q2
NMOS
Figure 11: Reference Circuit of RESET_N with NMOS Driving Circuit
Module
RESET_N
Reset
Logic
67
VDD 1.5V
200-700 ms
S1
TVS
R1
100k
33 pF
C1
Note: The capacitor C1 is recommended to be less than 47 pF.
The reset scenario is illustrated in the following figure.
V
IL
≤ 0.5 V
VCC
≥200 ms
Resetting
Module Status
Running
RESET_N
Restart
≤ 700 ms
Figure 1213: Resetting Timing of the Module