Radio Shack CCR-81 Reference Handbook

its reset state, and will start executing instruc-
tions from the ROM, starting at address 0000.
Notice that the only time pin 26 of the CPU is
ever low is a few milliseconds after power is
applied. Once C42 charges up past the logical
"1" level, pin 26 stays high until C42 is dis-
charged when power is removed.
Why is 253, a NAND gate, drawn as an OR gate?
Notice that pin 11 is high only when either of
the inputs are low. The NOT circles at the input
immediately tell you that this gate is looking
for a signal that is low to cause an output that is
high. Had the gate been drawn "correctly", then
it would not have been so obvious that the out-
put is active when high. This "functional" type
of logical symbolization is used throughout the
schematics.
Directly above the power-up circuit. there is a
similar
circuit. S2 is the Reset switch located on
the left side of the Board. Although there is a
power-on-delay type circuit at the input of this
network, it is not used as such. Notice that C57
is smaller than C42. Hence, in a power-up
"race", C57 would charge up faster than C42.
Assume that C57 is charged. Also assume that
pin 2 of 253 is high. This means that Z53, pin
3, will be low and Z37. pin 13, will be high.
With pin 17
of the CPU held high, everybody is
happy. if S2 is pressed. C57 will discharge
through the switch. The resulting low is applied
to pin 1 of Z53 and pin 3 goes high. Z37, pin
13, is then forced low. A low at pin 17 of the
CPU forces the microprocessor to restart at
address 0066. When S2 is released, R65 begins
to charge C57 until a logical high is applied to
pin 1 of 253. At this time, pin 17 of the CPU
goes
back high and the CPU starts executing
instructions from address 0066 in the ROMs.
S2 is used to get the microprocessor back on the
right road when it is "lost". This switch forces
the CPU toward a known address to enable it to
get on the right track. An example of a lost CPU
would be during a bad cassette load attempt. If a
cassette is loading and suddenly there is missing
information on the tape (caused by dirt or age),
the recorder may never stop. S2 can then be
pressed,
which directs the CPU out of the cas-
sette load routine and back into its ready mode.
The output at pin 18 of Z40 is called "Halt". In
Level
I BASIC this output should never be low.
It goes low
only when a software halt instruc-
tion is encountered by 240. In theory, this
instruction is not included in the ROMs. But
you might find pin 18 held low because Z40
thought it was told to halt. It could be due to
some data malfunction, or the CPU is lost and is
playing around with display data instead of
ROM data. In a case like this, S2 is not effective
in bringing the CPU home, because 253 is
latched up. About all you can do is shut the
Computer down and try again.
Notice that 253, pins 11 and 3, are also tied to
Z37, pins 2 and 3. Z37, pin 1, is an output line
labeled
SYSRES* (System Reset Not). It is
normally-high and only goes low during power
up (253, pin 11, causes this), or when S2 is
pressed (253 pin 3, causes this). SYSRES* is
used by the expansion interface and is not used
by the TRS-80 in Level I BASIC.
One last thing to mention about these two cir-
cuits: When you turn off power to the TRS-80
because of a lost CPU, wait at least 10 seconds
before you reapply power. If you do not wait,
C42 may not discharge completely and the CPU
may not go back to address 0000 during a re-
start. By waiting, C42 will discharge and upon
power-up, the system will start at the correct
ROM location.
WAIT, INT* and TEST
These three inputs to the CPU are pulled up to
VCC through resistors. Since they are active low,
you may not have any use for them. But you
should know what they are for.
The WAIT input, pin 24 of Z40, will slow the
CPU down if there are slow memories it must
access. If this line goes low, the CPU will go into
15

Radio Shack CCR-81 Specifications

General

Brand	Radio Shack
Model	CCR-81
Category	Desktop
Language	English