Table
of
Contents
Page
Introduction.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
7
System Block Diagram Description 9
The Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
12
THEORY
OF OPERATION 14
CPU
Address Lines
;'
16
CPU
Data
Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
17
CPU
Control Group 18
System RAM 24
Video Divider Chain 28
Video
RAMs.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
34
Video Processing
34
Keyboard 44
Input
and
Output
Port 44
System Power Supply 52
Level
II ROMs 55
,
ADJUSTMENTS
AND
TROUBLESHOOTING 57
THE OUTSIDE
WOR
LD 83
Memory Mapped External Device 86
Port
Based
External Device 88
Explanation
of
Expansion Port Signals. . . . . . . . . . . . . . . . . .
..
90
Pin
Connections
for
Expansion Port
Edge
Card
91
PARTS LIST 93
SCHEMATICS , 99
BASIC I ROMs 100
BASIC II ROMs 104
TRS-80
Master Schematic Diagram 111/113
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