System
RAM
According
to
the Block Diagram, System RAM
is
tied in parallel
with
the data bus
and
address
bus just like
ROM
and the Keyboard. The data
input
and
output
for
RAM
is
straightforward
enough;
MEM*
controls the buffers.
But
the
addressing
scheme
appears all screwed up.
How
can
the
CPU
address
a
minimum
of
4K
of
RAM
using
only
seven
address inputs? The answer
to
that
very good question
is
- multiplexing. The
address from the
CPU
is
multiplexed
into
the
RAM in
two
7-bit parts. The RAM's internal
logic takes the
two
parts
and
brings them togeth-
er
to
form
one
address
scheme
with
14 bits.
One part
of
the addressing
is
called RAS* (ROW
Address Select); the other part
is
CAS* (Column
Address Select).
Another
signal,
MUX
(Multi-
plexer), controls the switching function.
All
three
of
these signals
are
generated near the
CPU
on Sheet 1
of
the large Schematic.
MUX,
CAS*
and
RAS*
On
Sheet 1, find pins
21
and
22
of
the CPU.
Follow
the lines tied
to
these
two
pins down
to
NAND
gate
Z74.
If
we
get a
low
at
WR
(Mem-
ory
Write)
or
a
low
at
RD
(Memory Read), Z74,
pin 3 will
output
a high (called MREQ, Memory
Request). MREQ
is
tied
to
the clear inputs
of
Z69 and part
of
Z70.
These
devices
are
D type
flip-flops where the
MUX
*and CAS* signals
are
generated.
Figure 4 shows a waveform chart
for
this circuit.
Line A shows the master clock
input
to
the
flip-
flop~Line
B shows MREQ and Line C depicts
the
WR
output
from
the CPU. Assume
that
the
CPU
wants
to
write data
into
RAM.
As
shown
on Line
S,
MREQ
will
go
low. A short time
lat~r,
WR
will
go
low. Line D shows Z74, pin 3,
gomg high at the
same
time
WR
went low. The
flip-flops
now
have
a logical high applied
to
the
clear inputs.The flip-flops
are
free
to
operate,
c.o~trolled
by
the clock
waveform.
On
the
next
rising
edge
of
the clock, Z69 pin 5
will
output
the logic level that
was
pre~ent
at pin 2 the
24
instant pin 3 went high. Since pin 2
was
high
when pin 3 went high, pin 5
will
go
high. This
high
is
shown on Line
E.
Z69, pin 12
is
now
high;
so
on the next rising
edge
of
the clock,
pin 9
will
go
high. This
is
shown on Line
F.
Z70
is
ready
to
toggle.
On
the next rising
edge
of
the_clock, Z70, pin 6
will
go
low
(Q
went high,
so
Q must
HO
low). This
is
shown on Line H
of
Figure 4.
All
three flip-flops
have
changed states
since
WR
went low. The flip-flops
will
stay in
this state
as
long
as
WR
stays low.
When
WR
goes
high, the flip-flops
will
have
a
low
applied
to
their
clear inputs; and they
will
reset back
to
the clear condition.
Line
J
is
the RAS*
output.
As
you
can
see,
it
is
a direct function
of
MREQ
from
the CPU. Z72,
pins 4 and 5
are
RAS*'s buffer. Line K,
MUX
is
sourced at Z69, pin 9, through
buffer
Z72, pins
2 and
3.
Line L, CAS*,
is
buffered
by
Z72, pins
10 and 9,
and
is
a function
of
QCAS, at Z70,
pin 6.
Notice the following sequence
of
events: RAS*
goes
low
first.
MUX
then
changes
states. CAS*
then
changes
states one clock cycle later. First,
we
get
ROW
Address Select, then
MUX,
then we
get Column Select. Thus, the
first
part
of
the
address
we
give
the RAMs
will
be
the row
address.
We'll then
flip
the switch (multiplexer)
and
follow
with
the column
address.
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