Radio Shack CCR-81 Reference Handbook

CPU Control Group
OK, we now know how the CPU accesses the
address bus. We know the data bus is used to
gather data into the CPU or pass data out of the
CPU. What we do not know at this point is how
the CPU stores data in a memory or how it tells
the ROM or RAM that it is ready to receive
data. The CPU control group performs this task.
These signals are: RD, WR, OUT and IN.
RD (Read)
RD is Read control. This signal. when activated.
will tell other sections that the CPU is ready to
accept data. RD is generated at Z23, pin 6. Pin 5
is
connected to pin 21 of Z40, the RD (Read)
output. Pin 4 of Z23 is tied to pin 19. M REO
(Memory Request), of the CPU. Therefore,
when pins 19 and 21 of Z40 go low at the same
time. an RD output is generated. Notice the
backward symbol for an OR gate. It's drawn as
an AND gate. When we get MREO and RD,
then and only then will we get RD. We're look-
ing
for two lows on the input for a low output.
WR (Write)
WR is Write control. This signal, when activated.
will tell other sections that the CPU is ready' to
write data into one of the memory locations.
WR is generated at Z23, pin 11. Pin 12 of Z23 is
connected to MREO. Pin 13 of Z23 is tied to
WR (Memory Write), which is pin 22 of Z40.
When we get a low at the M REO output and a
low
at the WR output, then and only then will
we get a low at WR.
OUT (Output)
OUT is Output control. This signal, when acti-
vated, will enable circuitry to perform the cas-
sette save functions. It also is used to control
data movement from the TRS-80 to the Expan-
sion Interface.
OUT is generated at Z23, pin 3.
18
Pin 1 of Z23 is tied to the WR output on the
CPU. Pin 2 of Z23 is tied to IORO (Input!
Output Request) which is pin 20 of the CPU.
When
we get a low at WR and a low at IORO,
then and only then will we get a low at OUT.
IN (Input)
IN is Input Control. This signal, when activated,
will enable circuitry to perform the cassette load
function. It also is used to control data move-
ment from the Expansion Interface to the TRS-
80. IN is generated at Z23, pin 8. Pin 10 of Z23
is connected to IORO. Pin 9 of Z23 is tied to
RD. When we get a low at RD and a low at
IORO, then and only then will we get a low at
IN.
Control Group Bus
The Control Group must be buffered for use by
the different sections. Also, the bus may need to
be switched off at some time. Therefore, part of
Z22 is used to buffer the Control Group. Tri-
state control at pin 1 is tied to the address bus
control, and ENABLE* will affect the status of
the address and the control group bus in the
same manner.

Radio Shack CCR-81 Specifications

General

Brand	Radio Shack
Model	CCR-81
Category	Desktop
Language	English