Video Divider
Chain
The Video Divider Chain supplies the Video
RAMs
with
addresses
in a logical order
for
Video Processing. This chain also supplies the
horizontal and vertical sync
timing
pulses
so
that
the
Video
Processor can
build
the composite
waveform
for
the display.
Video
RAM address-
es,
horizontal and vertical sync, and Video Pro-
cessing
timing
are
all
direct
functions
of
the
master clock. Also included in the Divider Chain
is
the hardware necessary
to
generate 32-charac-
ter
line-lengths.
Although
level
I
can
not
access
the 32-character
format,
level
II
can.
Divider
Chain
Input Conditioning
If
the TRS-80 did
not
have
to
change character
line formats, the Divider Chain could have
been
tied
directly
into
the master clock. But, the
TRS-80 does have
two
formats
for
character
lengths. In the most
familiar
format,
the display
has
16 character-lines,
each
consisting
of
64
characters. This means there
are
1024 charac-
ter
locations in Video RAM which the Divider
Chain
must
access.
In the
other
format,
the
characters appear
twice
as
large. The display
will
show 16 character-lines
of
32 characters.
The Divider Chain must
access
only
512 Video
RAM locations. Switching
from
one
format
to
the
other
is
the
job
of
the I
nput
Conditioning
logic.
On Sheet 2
of
the large Schematics,
the
master
oscillator
circuit
is
surrounded
by
a D
flip-flop
(Z70L
a divide-by-12
counter
(Z58) and a
multi-
plexer (Z431. The D
flip-flop
is
wired
to
perform
a divide-by-two
function.
The mu
Itiplexer
is
wired
so
that
we
can
route the master clock
frequency,
or
the
clock
frequency divided
by
2,
from
the
flip-flop
to
the divide-by-12 counter.
Since there
are
two
character length formats,
there must logically
be
two
reference frequen-
cies; one
is
half
as
slow
as
the other. The master
oscillator supplies the divide-by-12
counter
with
28
a reference frequency in a
64
character
format.
The D
flip-flop
supplies the
counter
with
the
reference frequency in a
32
character
format.
The
multiplexer
is
doing the selecting,
so
what
is
controlling
it? Pin 1
of
Z43
is
a signal called
MODESEl
(Mode Select!. When
low,
MODE-
SE
L forces
Z43
to
be
switched
into
its 32
character position. When high,
MODESEl
forces
Z43
to
be
switched
into
its
64
character
position. Let's
look
at the
64
character mode
first.
Since
MODESEl
is
high, pin 3
is
"shorted"
to
pin 4
of
Z43. Pins 6 and 10
are
J'shorted"
to
pins 7 and 9. (Remember: a
multiplexer
is
an
electronic equivalent
of
a
multipole,
double
throw
switch.) Figure 5
is
a waveform chart
for
this
circuit.
At
Line
A,
the master
clock
is
shown at the
output
of
its
buffer,
Z42. Line B
shows the action
of
D
flip-flop
during its divide-
by-2
function.
The buffered
clock
is
applied
to
pin 3
of
Z43. Since the
multiplexer
is
switched
into
its
"1"
state, pins 3 and 4
are
the
same
sig-
nal and
counter
Z58
receives the 10 M
Hz
clock
frequency at pin 14.
Notice
that
flip-flop
output
Z70, pin 9,
is
tied
to
pin 2
of
Z43.
It
is
not
per-
forming
any
function
at this
time
since the
multiplexer
is
not
switched
into
its
"0"
state.
The
output
of
Z58
is
shown at lines
C,
D, E and
F in Figure
5.
The arrows in this figure
point
out
the
place where Z58's
outputs
are
all zero.
Notice
that
Lines C through F do
not
count
up
to
11, then
go
back
to
zero using straight binary.
Z58
starts fine: 0
....
1
....
2
....
3
....
4
....
5
....
On the
next
clock,
it
goes
from
binary 5
to
binary 8. From 8,
it
counts
normally
to
binary 13; then on the
next
cycle,
it
goes
back
to
binary zero.
Notice pins 6 and 7
of
Z58. These inputs
are
used
to
clear the
counter
to
zero.
If
you
find
CTR on Sheet
1,
you
will
see
it
comes
from
in-
verter Z42, pin 8, which controls the
CPU
ClK
divider.
Normally,
CTR
is
held low.
Only
during
automatic testing at the
factory
is
CTR allowed
to
go high and clear Z58.
You
might
find
"A"
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