RAS*
is
generated by the
CPU
at pin 19
(MREQ)' Whenever MREQ
goes
low, RAS*
goes
low;
and the RAMs will load the lower order
address
into
the row section. The
CPU
may
be
looking at system
ROM
when
MREQ
goes
low,
but
RAM
will
still receive RAS* and thus
be
"refreshed."
Normally, you would
not
be
too
concerned
about this aspect
of
the RAMs.
But
you
need
to
be
aware
of
the differences between a static
RAM and a dynamic RAM. Remember: Dynam-
ic RAM must
be
periodically addressed
to
enable
it
to
retain data. In the TRS-80, the RAM
is
refreshed once every
two
milliseconds.
RAM
Programming
You may
have
noticed Z71 during the discus-
sion
of
the RAM. Z71
is
a DIP shunt.
It
is
used
to
program the size
of
memory in a system. Find
pin 13 on the RAM.
Follow
it
down and you
will
see
that
it
is
tied
to
two
pins
of
DIP shunt
Z71. Pin 13
is
the
CE
(Chip Enable)
or
the
A6
address
input.
In a
41<
system, pins 4 and
130f
Z71
are
shunted.
RAM*
is
on pin 4,
so
RAM*
is
used
to
select RAMs.
But
in a
161<
system, 4 and
13
are
opened and pins 3 and 14
of
Z71
are
shorted. Instead
of
RAM*,
we'll get address line
A6
or
A 12 (depending on
multiplexer
status) go-
ing
to
pin 13
of
the RAMs. There
are
other parts
of
Z71 shown on the
left
side
of
the
multiplexer
(Z35 and Z51). Before troubleshooting a system,
you
will
need
to
know
the
size
of
RAM
that
the
system
uses.
If
Z71
is
"programmed"
wrong,
you may
find
yourself
with
RAM problems.
27
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