are shunted. RAM* is on pin 4
so
RAM* is
used
to
select
RAMs.
But in a 16K system, 4 and 13
are opened and pins
3
and 14 of
Z71
are shorted.
Instead
of RAM*,
we'll get
address line A6 or A12 (depending on multiplexer
status)
going to pin 13 of the
RAMs.
There are other
parts of X71
shown on the left side of the multiplexer, Z35
and Z51.
Before troubleshooting
a
system,
you will need to know
the
size
of
RAM
the
system
uses.
If
X71 is "programmed"
wrong, you may find yourself with RAM problems.
VIDEO DIVIDER
CHAIN
The
video divider chain supplies
the video
RAMs
with
addresses in a logical order for video processing. This
chain
also supplies
the horizontal and vertical sync timing pulses
so that the video
processor can
build
the composite wave-
form for the
display.
Video RAM
addresses, horizontal and
vertical
sync, and video processing timing
are
all
direct
functions of the master clock. Also included
in the divider
chain is the hardware
necessary to generate 32 character
line lengths. Although BASIC I can
not
access
the
32
character format, BASIC II
can.
DIVIDER CHAIN
-
INPUT
CONDITIONING
If
the
TRS-80 did
not
have
to
change character line
for-
mats, the divider chain could have been
tied directly into
the master clock. But, the TRS-80
does have two formats
for character lengths. In
the
most familiar
format, the dis-
play
has 16 character lines, each consisting of 64 characters.
This means
there are 1024 character locations in video
RAM
the divider chain must access. In the other format,
the characters appears twice
as
large. The
display
will
show
16 character lines of 32 characters. The
divider chain must
access only
512 video
RAM locations.
Switching from one
format
to
the other is the job of the input conditioning
logic.
On sheet
2 of the schematic section, the master oscillator
circuit is surrounded by a D flip-flop (Z70), a divide-by-1
2
counter (Z58) and a multiplexer (Z43). The D flip-flop
is
wired
to perform a divide-by-two
function.
The
multiplexer
is
wired
such that we
can route the
master clock
frequency,
or the clock frequency
divided
by
2,
from
the flip-flop
to
the
divide-by-1
2
counter.
Since there
are two
character
length
formats, there must
logically
be two
reference
fre-
quencies;
one is half again
as slow
as the other.
The
master
oscillator
supplies the divide-by-1
2 counter with
a
reference
frequency
in
a 64
character
format.
The D flip-flop
supplies
the
counter
with
the
reference frequency
in
a 32
character
format.
The multiplexer
is
doing the selecting,
so what
is control-
ling
it?
Pin
1 of Z43
is
a
signal called MODESEL (Mode
Select).
When low,
MODESEL
forces
Z43
to
be switched
into its 32 character
position.
When high,
MODESEL
forces
Z43
to
be switched into its 64 character position. Let's
look
at
the 64 character mode first.
Since MODESEL is high,
pin 3 is "shorted"
to
pin 4 of
Z43. Pins
6 and 10 are "shorted"
to
pins 7
and 9.
(Remem-
ber:
a
multiplexer is an electronic equivalent
of a
multi-
pole, double throw switch.) Figure
5 is a waveform
chart
for this circuit. At line A, the master clock
is shown at the
output of its buffer,
Z42.
Line B shows
the action of
D
flip-flop during its divide-by-2 function. The buffered clock
is applied to pin 3 of
Z43. Since the multiplexer is switched
into its
"1"
state., pins 3 and 4 are the same signal and
counter Z58 receives the
10
MHz clock frequency
at
pin
14.
Notice that
flip-flop
output
Z70,
pin
9,
is tied to pin 2
of Z43. It
is not
performing any function
at this time
since
the multiplexer is not
switched
into its
"0"
state.
The output of Z58 is shown at lines C, D,
E,
and
F
in
Figure 4. The arrows in this figure points
out the
place
where
Z58's outputs are all zero. Notice
that
lines
C
through
F
do not count up to
11,
then
go
back to zero
using straight binary. Z58 starts fine:
.... 1 .... 2 ... .
3 .... 4 .... 5 .... On the next clock, it
goes
from binary
5 to binary 8.
From
8,
it counts
normally to binary
13;
then on the next cycle, it goes back
to
binary zero.
Notice pins
6 and
7 of Z58. These inputs
are used to clear
the
counter
to
zero. If you find CTR
on sheet
1,
you
will
see it comes
from inverter Z42,
pin
8,
which controls the
CPU CLK divider. Normally, CTR is held low. Only
during
automatic testing at
the factory
is
CTR
allowed to
go
high
and clear Z58.
You
might find
"A"
and "D" Level Boards
with Z58, pins 6 and
7,
simply tied to ground.
Z58, pin
12,
is labeled DOT 1. Z58, pin
9,
is labeled DOT
2. DOTs
1
and 2 are "nanded" by Z24; and the resulting
output is shown in
Figure
5 at
line G. This signal is called
"LATCH" and is used in video processing.
Z43, pins
6
and
10,
are tied together and are connected to
Z58,
pin 8. The
resulting
output is
Z43,
pins
7
and
9,
will
therefore be the same signal.
Pin
9,
labeled
"CHAIN"
is the
divider
chain's
main
source.
Pin 7
of
Z43 is labeled
"C1
"
and is tied to pin 10 of
Z64,
one of the video
RAM
multi-
plexers. C1 will be used to address the video
RAM's
least
significant bit.
In the 32 character
format, Z43,
pin
1,
will be low.
There-
fore, pins
2,
5 and 1 1 will be "shorted"
to
pins
4,
7 and
9
respectively. (The electronic switch was flipped.) Now we
have
the
frequency source from Z70, pin
9,
tied to
counter
Z58.
Pin
7 of Z43 is held low all the time; and pin 9 of Z58
is now used as the source
labeled "CHAIN".
In
Figure
5,
lines H through K show
Z58's
outputs. Remember: We are
using line B in the
Figure
as the input to Z58 instead of line
A. Notice that Z58 is now being used
as
a divide-by-6
counter. The output
at
pin 9 is now "CHAIN" instead of
pin
8. Has
the
CHAIN frequency changed? No. In 64
64 character mode,
we had the master clock, divided by
12,
as the chain frequency.
That is
10.6445
MHz
divided
by
12
=
887.041
KHz. In
32 character mode, we had 1/2
master clock divided by
6,
as the chain. 10.6445
MHz
13
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