Radio Shack TRS-80 III - OPERATION; DRIVE MOTOR ENABLE (MOTORON); DIRECTION and STEP (DIR*) (STEP*); COMPENSATED WRITE DATA (CWO)

PART 3
OPERATION
INTRODUCTION
DRIVE MOTOR ENABLE (MOTORON)
This section contains the interface description and the elec-
trical
adjustments necessary for the Disk Drive.
INTERFACE ELECTRONICS SPECIFICATIONS
When this signal line logic level goes true (low), the drive
motor accelerates to its nominal speed of 300 rpm and stab-
ilizes in less than 250 mSec. When the logic level goes false
(high),
the Disk Drive decelerates to a stop.
• 5V
FIGURE 8. INTERFACE CONFIGURATION
When the Disk Drive is selected, a true (low) pulse with a
time duration greater than 200 nSec on the STEP line initi-
ates the access motion. The direction of motion is deter-
mined by the logic state of the DIRECTION line when a
STEP pulse is issued. The motion is towards the center of
the disk if the DIRECTION line is in the true (low) state
when a STEP pulse is issued. The direction of motion is
away from the center of the disk if the DIRECTION line
is in the false (high) state when a STEP pulse is issued. To
ensure proper positioning, the DIRECTION line should be
stable 0.1 /lSec (minimum) before the trailing edge of the
corresponding STEP pulse and remain stable until 0.1 /lSec
after the trailing edge of the STEP pulse. The access Illotion
is initiated on the trailing edge of the STEP pulse.
DIRECTION and STEP (DIR*) (STEP*)
74LS04 OR eQUIVALENT
• TRUE
'50 OHMS
'0 FEET
(3M)
TRANSMISSION LINE
ORIVER I
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L 7~6 ~r:...E~UIV~~~
All interface signals are TTL compatible. Logic true (low) is
+0.4 V (maximum). Logic false (high) is +2.4 V (minimum).
Figure 9 illustrates the interface configuration.
+ TRUE
It is recommended that the interface cable be a flat ribbon
cable, with a characteristic impedance of 100 ohms. (or
equivalent twisted pairs). Maximum interface cable length
is 10 feet (3 M).
Interface connector pin assignments and power connector
pin assignments are given in Table 1 and Table 2.
COMPENSATED WRITE DATA (CWO)
When the Disk Drive is selected, this interface line provides
the bit-serial WR ITE DATA pulses that control the switch-
ing of the write current in the head. The write electronics
must be conditioned for writing by the WR ITE ENABLE
line (refer to the WR ITE ENAB LE paragraph below).
INPUT CONTROL LINES
(See Table 1)
For each high-to-Iow transition on the WR ITE DATA line,
a
flux change is produced at the head write gap. This causes
a flux change to be stored on the disk.
SELECT LINES (DS1* - DS4*)
The SELECT lines provide a means of selecting and deselec-
ting a Disk Drive. These four lines (DS1 * - DS4*) select one
of the four Disk Drives attached to the controller. When the
signal logic level is true (low), the Disk Drive electronics are
activated and the Drive is conditioned to respond to step
or read/write commands. When the logic level is false (high)
the input control lines and output status lines are disabled.
When the double-frequency type encoding technique is
used (in which data and clock form the combined Write
Data signal), it is recommended that; when writing all
zeroes, the repetition rate of the high-to-Iow transitions be
equal to the nominal data rate, ±0.1%. The repetition rate
of the high-to-Iow transitions, when writing all ones, should
be equal to twice the nominal data rate, ±0.1%.
WRITE ENABLE (WG*)
A SE LECT line must remain stable in the true (low) state
until the execution of a step or read/write command is
completed.
The Disk Drive address is determined by SELECT lines 1
th rough 4 (or a DIP Shunt in the 1E position) on the PC
board. These lines provide a means of daisy-chaining a
maximum of four Disk Drives to a controller. Only one line
can be true (low) at a time. An undefined operation might
result if two or more units are assigned the same address or
if two or more SE LECT lines are in the true (low) state
simultaneously.
When this signal is true (low), the write electronics are pre-
pared for writing data (read electronics disabled). This
signal turns on write current in the read/write head. D<:\ta is
written under control of the WR ITE DATA input line. It is
generally recommended that changes of state on the
WRITE ENABLE line occur before the firstWRITE DATA
pulse. However, the separation between the leading edge of
WRITE ENABLE and the first significant WRITE DATA
pulse should not be less than 4 /lSec and not greater than
8 /lSec. The same restrictions exist for the relationship be-
tween the least significant WR ITE DATA pulse and the
101