3. SETTING FOR COMMUNICATION
IMCB03-E4
18
When host computer is selected from data sending to data receiving
When switching the host computer into reception from transmission, it must be confirmed that the
data was surely put on line. This is not observe the transmission buffer of host computer itself, but
confirming with shift register.
Next, the controller side secures the maximum time until the transmission line changes to the data
receiving side (until the controller is ready to send data) after the host computer has received the stop
bit corresponding to the final character. This maximum time corresponds to interval time.
If no interval time is set, the controller side may be set to the send state even when the host computer
side is not set to the receive state. As a result, no communication is conducted correctly. In addition,
set the interval time so as to match the host computer.
When host computer is selected from data receiving to data sending
Polling procedure "Response wait time after BCC send" or selecting procedure "Response wait time
after [ACK] or [NAK] send" is processing time required during controller data sending. Therefore,
select the host computer from receiving to sending after the lapse of the above time.
As for the necessary processing time, refer to the table of page 16.
(4) A transmission error may occur with the transmission line disconnected, shorted or set to the high-
impedance state. In order to prevent the above error, it is recommended that the fail-safe function
be provided on the receiver side of the host computer. The fail-safe function can prevent a framing
error from its occurrence by making the receiver output stable to the MARK (1) when the
transmission line is in the high-impedance state.
(5) The nonvolatile memory (EEPROM) for data backup has limitations on the number of memory
rewrite times (approx. 100,000 times). Avoid using the memory to frequently change the set value
via communication.
8 bit
8 bit
Transmission
data
Transmission
buffer
Shift register
Transmission
data
Transmitting 1 bit each
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