RK3288 Hardware Design Guide
8 DDR Controller & DRAM
8.1 Schematic
RK3288 has dual channel 32bits DDR controllers, DDR0 and DDR1. They share the
same configuration. Taking DDRO channel for example:
Four groups of data cables（DATA0—DATA31）, four DATA MASKS（DQM0--DQM3），
four pairs of differential lines DATA STROBES（DQS0P/ DQS0M—DQS3P/
DQS3M）.All of them can be divided into four groups：
GROUP A：（ DATA0—DATA7，DQM0，DQS0P/ DQS0M）
GROUP B：（ DATA8—DATA15，DQM1，DQS1P/ DQS1M）
GROUP C：（ DATA16—DATA23，DQM2，DQS2P/ DQS2M）
GROUP D：（ DATA24—DATA31，DQM3，DQS3P/ DQS3M）
The rest signals can be divided into three groups：
GROUP E：Address： ADDR0—ADDR14
GROUP G：Control：including WE, CAS, RAS, CS0, CS1, CKE0, CKE1, ODT0, ODT1,
BA0, BA1, BA2, etc.
GROUP F：Clock：differential pair of CLK and CLK
DDR controller outputs address and control signals when occurring falling edge in
CLK, and latches the status of address and control buses when occurring rising
edge in CLK. So the sequence between CLK and address/control must fit the best
setup/hold timing
For address signals, no matter DDR3/3L or LPDDR2/3, none of them is permitted to be
exchanged with each other, the same for control signals.
When exchanging between group(A, B, C, D) data , DATA MASKS and DATA STROBES
are also responded to be exchanged, as shown in Fig 8-1：
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