Sage II - Page 70

SAGE II
SERVICE
KIT
CPU
BOARD CIRCUtrT
DESCRIPTIONS
PAGE 2
OF
SCHEMATIC DIAGRAMS
(cont)
INTERR.UPT
CONTROTLER
The tntel-ligent
Lnt.errupt
control-ler U73
is
an
8259'5.
I^lhen
one
or
more
of
{fr's lnterrupt lnputsr
IR0-IR7,
go acttve high
lt sends an
lnterrupt
to
the
processotrs
lnterrupt
encoder on
page
l.
Thts
slgnal
ls
called
lCI-
after tt ls
lnverted by
the
74LS04
buffer
tJ72
pins
5
and
6.
The
processor
lnay
access
this
device to
determine
the
source of
the
interrupt
or
to
program
the
priarl-ty
mask.
TTHBR.S
T\^ro
82-53-5
programmab]-e
interval timers u75
and
tJ7
4 are
utll
rzed
ln
the
Sage II.
U75
generates
the two baud
rates
for the
USARTS.
These
signals are BRl+
and BR2+
and are used
at the
serial
ports
on
page
6.
Each devl-ce contains
3
lndependent
16-bit
counters,
Two of these
counLers
are used to
produce
the baud
rates. The use
of the
remainlng
cotrnters
is
dependant on
appropriate
software.
Typlcal
uses
are event
scheduler and
reaL time
clock,
Sections
IV.4.6
and IV.4.7
of the SAGE
II Onrners"
Manual descrlbe
the
software
available
to
access
these
t
imers.
XVII"O3 PACE 3
OF SCHEI.IATIC
DIAGRA}TS
:
Thts sectlon
contains
the RAI'I
parity
interrupt signal
generation,
RAM
refresh and refresh arbitratlon,
and RAFI control
clrcultry.
PARITY IT{TERRUPT
The circult
in the
upper left corner
of
this
page
ls the
parity
error
lnterrupt
generatLon
cLrcult"
Ttre
parlty
reset signal
PRES-
comes
from
U39
pin
l&
on
page
6.
PRES-
goes
low
during
inltiallzatl-on,
ls
lnverted
at
74LS04
U37
ptr-ns
9
and
8,
and
appears
high at the
preset
lnput
pln
10
of
tlre
parlEy
latch
U51
which
ls a
74L574
D-type
positlve
edge
triggered
fl lp flop,
This makes the
a
output of
U51
inactlve
hlgh
whlch
ls the
ncrrrnal- state and lnputs a hlgh to
74LS00
U50
pin
12.
In
thls
normal
state the
NAND
gate
U50
pins
11-13
looks like an
Lnverter between
plns
i3
and
tr l.
The lnput at
U50
pin
13
is
RAl,l-l
whlch
goes
low after
a
RAM
access and thus causes a
posltlve
edge
clock
to
U51
at
pin
I l.
The
i"nputs
ar
U50
plns
& and
5
orlginate
at the ram clrcuit
page
4.
Parity
flag 1ow
PFL- and
parlty
flag high
PFH-
are both
actlve low.
The
low
and
htgh refer
to upper and lower bytes of RAM.
l
f
elther of these
signai-s are actlve
low
then
ptn
6
of
U50
goes
hlgh.
If
the
buffereei reacl
/wrice
signal
BRW+ from
page
1ls
hlgh tndlcatlng
a read cycle
then the
output of U50
at
pln
I
w111
go
low.
At
the
end
of
the cycle when
RAI'+|-
goes
1ow the low at
U-51-12
gets
clocked through to
U51-9
and
also
appears
at
p{n
4
of nonlnverting buffer
U48
as
actl-ve
low
PRTY*" This
al-so
places
a
low at
U50
pin
LZ
and does
not
allow
the
flip
f
-op
U5 tr
to
be
clociced again until it 1s
preset
by
PRES-
ef
fectlvely
l-atching
the
PRTY-.
interrupL
decoder"
PRTY-
goes
to
U36-4
on
page
I
whlch ls the
6l