Sage II - Error Lookup List; BIOS Channel Error Codes

SAGE
II
SERVICE
KIT
CPU
BOARD
CIRCUIT
DESCRIPTIONS
PAGE
3
0F SCHEI'IATIC
DIAGRAI'{S
(conr)
I.TET,IORY
BA}IK
SELECTION
Memory
bank
selectlon
ls
accompllshed
by
decoding
address
llnes
Ll7,
&
A18
wlth
one
half
of a
74LS139
(U47).
Ttre
decoded
outputs
are
gared
ro
the
RAS
lines
of
the
approprlate
memory
banks with
I/2 of
an
74LSZ4L
(U+0)
during
the
active
tlme
of
RAI'I+.
The
other half
is
used
to
gate
the
RAS
slgnal
to
the
memorles
during
refresh
cycles.
UE}IORY
REFRESH
CONTENTION
ARBITRATION
Refresh
cycles
are lnitiated
every
15.625 usec from
the
64 l(hz
refresh
clock.
The refresh
request
ls
latched
lnto
the first
sectlon
of
the
D
fllp
flop
(U34).
The
next
falltng
edge
of AS+
(gared
with
rhe
g
Mhz
clock)
clocks
the
refresh
request
into
the
refresh grant
fl1p
flop
(U34-2)
tnttlatlng
a
memory
refresh.
The
output from
the
refresh gr".ti
fllp
flop
(plns
5
&
6
of
U34)
goes
ro
three
places.
Flrst
tt
disables
RAI'I+
generatlon
wlth a
low
on
pin
ll
of
Ul5.
Second lt
generates
a hlgh
on the
output
(ptn
6)
of
U41
whlch
Lncrements
the
refresh
counter, generates
a
low
on the
output
(ptn
4)
of
U33
whlch
enables
the
refresh
address
to
the
ROI^I
address
llnes
through
Ulz
whlle
stmultaneously
dlsabllng
both
U10, &
Ull
from
placlng
any
addresses
on
the
ROW address
llnes.
This
is
a
250ns
pulse
generated
when
RF+
goes
hlgh
settlng
the
output
(pln
6)
of
U4l
(AND)
hlgh
unrtl
the
tow
st[nal
propagates
through
the
delay
line
(260ns)
setting
the
output
back
low.
Thlrd
a
190 nsec
pulse
with
a delay
of
70
nsec
from
RF ls
generated
with
the
70
nsec,
&
260ns tap
on the
delay
line,
one
section
of
U33
(plns
1
to
2) and
one
sectlon
of
U32
(pins
l, 2, &
3)
whlch
ls
the
actual
RAS
slgnals
to
the rams
for
refresh.
The
Refresh
RAS ls always
enabled
to
the
RAS
llnes
of the
RAl,tS
whenever
RAI.,I+ is
low.
uErioRY
ADDRESS
SBQUENCE
A11
memory
address
cycles
start wlth
the
rlslng
edge
of
AS+.
At thls
polnt
the
address
bus has
had a
valid
address
for
about
30
nsec.
4
maln
events
start
on the
rislng
of
AS+. First
the approprlate
read
or
wrlte
data
buffers
to
the rams
are
enabled
through
pins
3
of
U4l,
or
ll of
1J32.
Second
the
signal for
the
eventual
CAS ls
started
through
the
60
nsec
delay
l-lne.
Thlrd
the
RAS buf f
er
(
U46)
ls
switched
f rom
the
refresh
mode to
the
data
node
sending
a
RAS- to the
selected
bank
of
memory.
Fourth
the 1ow
byte address
buffer
is
dlsabled
(ul0)
lnmedlately
followed
by Ehe
htgh
byte address
buffer
belng
enabled
(Utt;
onto
the
Address
1lnes
of
the
RAM'S to
walt for
the eventual
CAS slgnal
when tt
gets
through
the
delay llne.
the falllng
edge
of
AS+
clocks any
parity
error generated
durlng
the
memory
cycle
to the
parlty
l-nterrupt.
62