Samsung CLP-610ND - Page 28

Product spec and feature
Samsung Electronics
Service Manual
2-19
• DMA Controller : 3 Channel
• HPVC : 4 Channel Dual / Single Beam
• UART : 4 Channels (Debug, OPE 2 Channel used )
• Interrupt : 4 External, 64 Internal
• TIMER : 6 System Timer
Mips + SPGPXm Architecture
• CPU : Mips IV 533Mhz (I-Cache : 16KB, D-Cache : 16KB, Secondary-Cache : 256KB)
• SDRAM Controller : 4 bank DDR1 SDRAM (2 DIMM Used), 120Mhz System Bus
• ROM Controller : 4 Channel NOR, 1Channel NAND ( 1 Channel NOR Used)
• I/O Controller : 6 Channel
• DMA Controller : 4 Channel
• HPVC : 4 Channel Dual / Single Beam
• UART : 5 Channels (Debug, OPE 2 Channel used)
• Interrupt : 10 External
• TIMER : 6 System Timer
Memory Interface
• ROM :
- Nor Flash used (16MB)
- Interface With Chorus 3/SPGPXm ROM Controller
• SDRAM :
- Size : CLP-610ND(DDR2) : Default 128MB (Option 128MB/256MB)
CLP-660N/660ND(DDR1) : Default 128MB (Option 256MB/512MB)
• EEPROM :
- Size : 64kb
- Interface With Chorus 3/SPGPXm I2C Controller
• CRUM :
- Size : 256Byte
- Interface With Chorus M I2C Controller via Deve Joint B’D