Sharp FO-4450 - Page 80

FO-4450U/FO-CS1
5 – 6
LC272D0BT-WA6 (IC6) Terminal description (1/2)
PIN I/O Name Function PIN I/O Name Function
1 VSS Ground 55 P VSS Ground
2 B D7 Data bus 56 O XNICACK Acknowledge signal for NIC
3 B D6 Data bus 57 I XNICINT Interrupt request from NIC board
4 B D5 Data bus 58 O XNICCS Chip select (NIC Board)
5 B D4 Data bus 59 O XJBG1 Reserved
6 B D3 Data bus 60 O XJBG0 Reserved
7 B D2 Data bus 61 B MAD0 Data bus of page memory
8 B D1 Data bus 62 B MAD1 Data bus of page memory
9 B D0 Data bus 63 P VDD Power supply
10 I 64 P VSS Ground
11 I XCS4 65 B MAD2 Data bus of page memory
12 O DMA acknowledge (Ch0) 66 B MAD3 Data bus of page memory
13 O XDACK1 DMA acknowledge (Ch1) 67 B MAD4 Data bus of page memory
14 O XDRAK0 DMA request acknowledge (Ch0) 68 B MAD5 Data bus of page memory
15 O XDRAK1 DMA request acknowledge (Ch1) 69 B MAD6 Data bus of page memory
16 I XDREQ0 70 B MAD7 Data bus of page memory
17 I XDREQ1 71 B MAD8 Data bus of page memory
18 P VDD Power supply
72
VDD Power supply
19 P VSS Ground 73 P VSS Ground
20 O XFLCS Chip select (Flash memory) 74 B MAD9 Data bus of page memory
21 I XFLSHINTA Interrupt request of flash memory 75 B MAD10 Data bus of page memory
22 I XFLSHINTB Interrupt request of flash memory 76 B MAD11 Data bus of page memory
23 O XINT0 Interrupt request signal 77 B MAD12 Data bus of page memory
24 O XINT1 Interrupt request signal 78 B MAD13 Data bus of page memory
25 O XINT2 Interrupt request signal 79 B MAD14 Data bus of page memory
26 O XINT3 Interrupt request signal 80 B MAD15 Data bus of page memory
27 O XPGMCS 81 P VDD Power supply
28 O XWROUT 82 P VSS Ground
29 O XRDOUT 83 O SDCLK Clock of page memory
30 O XWAIT Wait request signal 84 O DQMUL Data mask of page memory
31 I XBUSYDP Busy signal of Dual port RAM 85 CKE CK enable of page memory
32 I XMDMINT1 86 O CASB CAS of page memory
33 I XMDMINT0 87 O RASB RAS of page memory
34 O XMDMCS1
Chip select (Modem Chip 1)
88 DWEB Write strobe of page memory
35 O XMDMCS0 Chip select (Modem Chip 0) 89 XCSDRM0 Chip select of page memory
36 P VDD Power supply 90 VDD Power supply
37 P VSS Ground 91 P VSS Ground
38 I XINPRT 92 MA0 Address bus of page memory
39 O XOUTPRT Print block clock out 93 O MA1 Address bus of page memory
40 P VSS Ground 94 O MA2 Address bus of page memory
41 I TODB Top of data 95 O MA3 Address bus of page memory
42 I HSYNC Synchronous signal of horizontal anxious 96 MA4 Address bu s of page memory
43 O PDATA Print data 97 O MA5 Address bus of page memory
44 I XJBGINT1 Reserved 98 MA6 Address bus of page memory
45 I XJBGINT0 Reserved 99 VDD Power supply
46 I XSGAINT Interrupt request from modem chip 0 100 P VSS Ground
47 I XSBGA Chip select (Sub Gate array) 101 O MA7 Address bus of page memory
48 I JBGDREQ00 Reserved 102 O MA8 Address bus of page memory
49 I JBGDREQ01 Reserved 103 O MA9 Address bus of page memory
50 I JBGDREQ10 Reserved 104 O MA10 Address bus of page memory
51 I JBGDREQ11 Reserved 105 O MA11 Address bus of page memory
52 O XJBGACK1 Reserved 106 O MA12 Address bus of page memory
53 O XJBGACK0 Reserved 107 O MA13 Address bus of page memory
54 P VDD Power supply 108 P VDD Power supply
P
Chip select (Erea 0)
Chip select (Erea 4)
DMA request (Ch0)
Chip select (Program memory)
Write strobe signal
Read strobe signal
Interrupt request from modem chip 1
Interrupt request from modem chip 0
Print block clock in
O
DMA request (Ch1)
XCS0
XDACK0
P
O
O
O
O
O
P
P
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