FO-4450U/FO-CS1
5 – 7
LC272D0BT-WA6 (IC6) Terminal description (2/2)
PIN I/O Name Function PIN I/O Name Function
109 P VSS Ground 163 P VSS Ground
110 I TEST0 Test pin 0 164 O TXAI1 Current control 1 (Phase A)
111 I TEST1 Test pin 1 165 O TXAI0 Current control 0 (Phase A)
112 I XINSC Image block Clock in 166 O CRNT0 Current change signal 0
113 O XOUTSC 167 O CRNT1 Current change signal 1
114 P VSS Ground 168 O XLBE Low byte(D7-D0) enable signal
115 O TOUT Test pin 169 I XRESET System Reset Signal
116 O LININT Monitor for line interval signal 170 O XMANRES Manual Reset Signal
117 O SAMP Monitor for sampling point 171 O XNANDOPCS Chip select (Optional memory)
118 O Line shift clock (CIS) 172 O XNANDSTDCS Chip select (Standard memory)
119 O CLK1 Transfer clock (CIS) 173 O XNANDRD Read signal (Nand flash)
120 P AVDD Power supply (Analogue) 174 O XNANDWR Write signal (Nand flash)
121 P AVSS Analogue Ground 175 O XWP0
122 I ADREFL 176 O XWP1
123 I TEMP 177 O ALEO Address latch enable (Flash memory)
124 I AVO Video signal for scanning 178 O CLEO Command latch enable (Flash memory)
125 O ATAPH 179 I SHCK CPU Outer bus Clock
126 P AVDD Power supply (Analogue) 180 P VDD Power supply
127 P AVSS Analogue Ground 181 P VSS Ground
128 P VDD Power supply 182 I RXW Read/Write signal
129 P VSS Ground 183 I XBS Bus cycle start signal
130 O PLTSW Plate SW detect 184 I A25 Address bus bit25
131 O BKLON Back light on/off control 185 I A24 Address bus bit24
132 I SEN7 Key sense signal 186 I A23 Address bus bit23
133 I SEN6 Key sense signal 187 I A22 Address bus bit22
134 I SEN5 Key sense signal 188 I A21 Address bus bit21
135 I SEN4 Key sense signal 189 I A20 Address bus bit20
136 I SEN3 Key sense signal 190 I A13 Address bus bit13
137
IS
EN2 Key sense signal 191
IA
12 Address bus bit12
138 I SEN1 Key sense signal 192 I A11 Address bus bit11
139 I SEN0 Key sense signal 193 I A10 Address bus bit10
140 B LD15 LED 194 I A9 Address bus bit9
141 B LD14 LED 195 I A8 Address bus bit8
142 B LD13 LCD drive signal 196 I A7 Address bus bit7
143 B LD12 LCD drive signal 197 I A6 Address bus bit6
144 P VDD Power supply 198 P VDD Power supply
145 P VSS Ground 199 P VSS Ground
146 B LD11 Reserved 200 I A5 Address bus bit5
147 B LD10 Reserved 201 I A4 Address bus bit4
148 B LD9 Reserved 202 I A3 Address bus bit3
149 B LD8 Reserved 203 I A2 Address bus bit2
150 B LD7 LCD drive 204 I A1 Address bus bit1
151 B LD6 LCD drive 205 I A0 Address bus bit0
152 B LD5 LED/LCD drive 206 B XWE0 D7-D0 select signal
153 B LD4 LED/LCD drive 207 B XOPDEN Bus buffer enable control
154 B LD3 Key matrix select/LED/LCD drive 208 B D15 Data bus bit15
155 B LD2 Key matrix select/LED/LCD drive 209 B D14 Data bus bit14
156 B LD1 Key matrix select/LED/LCD drive 210 B D13 Data bus bit13
157 B LD0 Key matrix select/LED/LCD drive 211 B D12 Data bus bit12
158 O TXB Current direction (Phase B) 212 B D11 Data bus bit11
159 O TXBI1 Current control 1 (Phase B) 213 B D10 Data bus bit10
160 O TXBI0 Current control 0 (Phase B) 214 B D9 Data bus bit9
161 O TXA Current direction (Phase A) 215 B D8 Data bus bit8
162 P VDD Power supply 216 P VDD Power supply
Image block Clock out
Low reference voltage (ADC)
Temperature detect
High reference voltage (ADC)
Write protect (Standard)
Write protect (Optional)
SH
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