Sharp HT-CN410DVH - Page 49

HT-CN410DVH
49
IC201, Programmable Multimedia and DSP Processor (ES6809PADF)
ES6809 Pin Description:
Names Pin Numbers I/O Definitions
VD33
1, 11, 20, 36, 45, 53, 63, 80, 97,
122, 130, 156, 182, 197
P I/O power supply.
AUX0 2 I/O Host control 0.
AUX3 3 I/O Auxiliary port 3.
RESET# 4 I Reset (active-low).
AUX1 5 I/O Host control 1.
DMA11:0 6:9, 12:18, 21 O DRAM address bus.
VSS
10, 19, 27, 35, 44, 52, 62, 72, 79,
87, 96, 123,133, 138, 183,
196, 201, 208
G Ground.
DRAS2-0# 22, 23, 26 O DRAM row address strobes (active-low).
DCS1-0# 24, 25 O DRAM chip selects (active-low).
VDD 28, 73, 88, 134, 202 P Core power supply.
DCAS# 29 O DRAM column address strobes (active-low).
DOE# 30 O DRAM output enable (active-low).
DWE# 31 O DRAM write enable (active-low).
DSCK 32 O Output clock to DRAM.
DQM 33 O Data input/output mask.
DB15-0 34, 37:43, 46:51, 54,55 I/O DRAM data bus.
LA21-0
56:61, 64:67, 69:71,
74:78, 81:83, 101
O SRAM address bus.
LWRLL# 68 O SRAM bus write enable (active-low).
LCS3-0# 84:76, 89 O SRAM bus chip select (active-low).
LD7-0 90:95, 98, 99 I/O SRAM data bus.
LOE# 100 O RISC port output enable (active-low).
SPDIF_OUT 102 O S/PDIF output.
SPDIF_IN 103 I S/PDIF input.
VD33PLL 104 P Power for PLL blocks.
VS33PLL 105 G Ground for PLL blocks.
VREF
106
I Internal voltage reference to video DAC.
YUV1 O YUV pixel 1 output data.
PIXOUT1 O CCIR656 output pixel 1.
COMP
107
I Compensation input.
YUV3 O YUV pixel 3 ouput data.
PIXOUT3 O CCIR656 output pixel 3.
RSET
108
I DAC current adjustment resistor input.
YUV4 O YUV pixel 4 output data.
PIXOUT4 O CCIR656 output pixel 4.
FDAC
109
O VideoDAC output. Refer to description and matrix for UDAC pin 115.
YUV7 O YUV pixel 7 ouput data.
PIXOUT7 O CCIR656 output pixel 7.