Sharp HT-DV30H

HT-DV30H
8 – 2
IC4 VHiiS42S164F6 : 16 Bit, SDRAM ( iS42S16400F ) ( 1/2 )
BLOCK DIAGRAM
Figure 8-3 BLOCK DIAGRAM OF IC
CLK
CKE
CS
RAS
CAS
WE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A11
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM
DQ 0-15
V
DD/VDDQ
GND/GNDQ
12
12
8
12
12
8
16
16 16
16
256K
(x 16)
4096
4096
4096
ROW DECODER
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER