Pin
used
for
minimum
mode.
-lIviwl".
bel!oTable
11
..
b
,j:)O
l.
t:
s.
k!inNo.
Pin name
Function
1
,.
28
M/la
Deta
tra
nsfer
t
"n
ai
1
p"
ri-
,-{"
111
",':'29
ui
ad
tiff
!1
'.
, "
1
24
25
27
26
31
('
I
30
control
output
WR
Wirte
control
output
1NTA
Interrupt
ac-
knowledge
output
ALE
Address
latch
enable
output
DT/R
Deta send/receive
control
output
DEN
Data enable
output
HOLD
Hold
request
input
HLDA Hold acknowl·
edge
output
Pins
used
for
maximum mode.
Table 11·c
Pin
No.
Pin
name
Function
26
SOS251
Status
output
1
28
30,31
RQ/GTO
Request/grant
RQ/GT1
input/output
29
LOCK
Lock request
output
24,25
QS1,
QSO
Queue status
output
IN/OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN/OUT
OUT
IN/OUT
OUT
OUT
-
MZ-5600
Description
Indicates whether
the
CPU
is
accessing
the
memory or an
I/O
device.
Indicates
the
timing
of
write operations
to
an external memory or I/O device.
Used as a
strobe
to
read interrupt vectors
on
the
data
bus during
the
interrupt
acknowledge cycle. Also indicates an interrupt acknowledge
to
the
device
in
request
for
interrupt.
Strobe
used
to
load address information (which
is
output
from
the
CPU
on
time-division scheme)
into
external latches.
Indicates
the
direction
of
data transfer
to
an external data bus buffer.
Enables
the
external data bus buffer.
When receiving a
Hold request,
the
CPU
relinquishes bus access
authority
and
enters
the
Hold
state
immediately after completing
the
current
machine cycle.
Indicates
that
the
CPU acknowledged
the
Hold request
and
relinguished bus
access
authority,
to
the
device
in
request.
Description
S2
S1
SO
0 0 0
.
Interrupt
acknowledged.
0 0
1 Read I/O port.
0
1
0
Write I/O port.
0 1 1 Hold
1 0 0
Fetch instruction.
1
0
1 Read memory.
1 1
0
Write memory.
1 1 1
Passive
cycle.
Used
to
receive Hold request
and
output
Hold acknowledge when a device
other
than
the
CPU wants
to
use
the
local bus. The RQfGTO pin has a higher priority
over
the
RQfGT1 pin.
Used
to
inhibit
other
system bus masters accessing
the
system bus when
the
CPU
wants
to
use
the
system bus.
--
Indicates operations performed
at
the
instruction queue:
QS1
QSO
0 0
No
operation.
0
1
Fetches
the
first
byte
(OP
code) of an instruction.
1
0
Clears
the
contents of
the
queue.
1 1
Fetches
the
second and subsequent bytes of
the
instruc,
tion.
-17-
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