Sharp MZ-5500 - Page 19

OBus control circuit
Fig.1-3 shows the block di agram of the MZ-5500/5600 bus control circuit.
\.Jhen the 8086 is operate . cl undet the maximum mode, command (RD, WR, 1NTA) is
issued in a form of a status . (50-52) which is decoded by the 8288 to send
the control signal . to the memory and the 1/0 de~lce.
IIOB6
(PLI
<:0-
TI
TI
8288
SO
sr
TI
iliiOC
N~lC
AJoI ~c
/OkC
/O~("
A/O'tttC
IN1A
Memory read contro! output
Memory ~rite control output
Advanced 1/0 write control output
1/0 re~d contro! output
1/0 write contro} output
Advanced memory ~rite contro! output
Interrupt acknow!edge
Fig.J-3 Bus control circuit block diagram
Tabl~ 1-3 8288 input vs output
52
51
SO Output
0 0 0
lNTA
0 0 1
lORC
0
1 0
IOWC, A10WC
0
1
1
Hold
1 0 0
MRDC (command fetch)
1
0
1 MRDC
~"
1. 1 0
MWTC, ANWC
1 1
1
Passive
,
-0....- ___ -.-. .... WAX 35 41:"'" WA,X 35
ClK
iiRöC . TcTi«:
AWie . AiO"WC : .
" \ " :,' I' '.
INTA
: ': :" .
, -: LJ~WAX,3S:
" '
I ,
, ~~NAX3S..j :"WAX45
During a write :
mterru pt 7' ---"""--'---JJ~ I \ :
~- __ --J':'l.b ~~-,,: -\-WAX-(5- . MAX45 '
" During a raad -.. l
D1/R
~'n"':"'" MAX . ",
oe '"
• -:
'
;.- NA>",
I
Fig.1-4 Timings
o RESET, READY circuit
RESET
J
Für reset of the 8086 CPU, tI,e alarm signal from the power supply unit and a
rising edge at the time of power on are detected by the CR network. RESET
signal to tile CPU is internally synchronized with CLK ' by the 8284A. For the
alarm timing, refer to the paragraph which discussed the power supply.
READY
For the MZ-550lVS600 is normally a non-ready . system, the ready signal is
returned to the CPU against a valid accessing. Actually, memory and 1/0
decode signal is inputted to the 8284A, but, RDY is delayed in the wait
timing circuit in synchronization with CLK for a device that requires wait.
\.Jhen the 1/0 aIld memory of the XACK area is accessed, the ready signal of
timeout . is automatically returned unless XACK is returned within 130ps, and
I.
NMI i8 issued to the CPU at the same time.
Fig.1-5 shows the block diagram of the MZ-5600 RESET and READY circuits and
Table 1-4- shows wait count required for device. llowever, on the MZ-5500, the
L SPD signal (fo r wait co u nt adjustment acco r ding to th e choic e of 5Mllz/8MlIz
(' l oc k) sh o wn in th e bl ock di ag ra m is not applicable, and signal nClm e TG555
is c hang ed to ANS55. Wait co unts ar e for the 5MHz mode in T abl e 1- 4.
\b