Sharp MZ-5500 User Manual

(8) VRAM bus control
< (j) VRAM bus cycle
. 1", VRAM bus cycle is divided into GDC and CPU cycles,
as shown below. The CPU timing signal (VDC1 internal
• signal) samples the RAS (GDC) at the trailing edge of
r; the 2xCCLK signal.
{
2XCCLK
GDC RAS
CPUtiming~ CPU
)
Display or
refresh cycle
GDC [CPU
GDC
CPU
Display
Refresh
. {pa~ )
e,o. DC RAS ro r--I Drawing
\.;" CPUtimi~ 1 _________ ---" L cycle
~ CPU GDC (CPU
0..,1"11
Fig. 92
The VRAM can be aecessed from the CPU when the
CPU timing is high, and can be aecessed from the GDC
when it
is low.
CPU BUS
CDE(VDC1)
G
LS244
LS374
GDC BUS
TMM4116 or
MB81416
-
MZ-5600
(jj) VRAM data bus
The following figure provides
the VRAM data bus
logic.
1) During display
or RAM refresh cycle, the VDEO-2,
GDE, and CDE are all high, leaving the bus buffer
outputs off.
2) For reading aecess from
the CPU, the pertinent
VDE is set low and the CR L of the LS374 is set
high,
to latch read data.
3) For writing access from the CPU, the CDE and the
corresponding VDE are set low.
4) For drawing access from the GDC, the GDE and
corresponding
VDE lire set low. However, if A16
and A 17
of the GDC are both one, the GDE remains
at high since the mapping RAM area is accessed.
The DBD
is normally a RAM read line, and is turned
into a RAM write line only when aecessed from the
CPU or GDC.
DBD(VDC1)
If the reset line for VDC1 is set low, the GDE, CDE,
and
VDEO-2 are all set high.
DBD(VDC1)
~
Shift
Ir----------+---- Register
1,----
r------
,...------,...----.,
r - - - - - - ,...------.
I
I
RAM
~ - - - - - -\----1
I
I
:------+----1
r - - - - - -+-----1
I
I
.. ----- -'------'
I
I
RAM
I- - - - - - -+-----1
I
I
L.._ ----+----1
I
I
~- ----+-----1
I
I
.- ---- - -'----~
-67-
I
•
RAM
:------+_---1
I
~------+-----I
I
I
~ - - - - -1-----1
I
I
L ______ '-- __ --'
Fig. 93

Sharp MZ-5500 Specifications

General

Brand	Sharp
Model	MZ-5500
Category	Desktop
Language	English