102
4.4 FLAGS
Each
of
the two Z-80A CPU Flag registers contains six bits
of
information which are set or reset by various CPU
operations. Four
of
these bits
are
testable; that is, they are used
as
conditions for jump, call or return instructions.
For
example a jump may be desired only if a specific bit in the
flag
register
is
set. The four testable flag bits are:
1)
Carry Flag (C) - This flag
is
the carry from the highest order bit
of
the accumulator.
For
example, the carry
flag will be set during an add instruction where a carry from the highest bit
of
the accumulator
is
generated.
This
flag
is
also set
if
a borrow
is
generated during a subtraction instruction. The shift and rotate instructions
also affect this bit.
2) Zero Flag (Z) - This
flag
is
set
if
the result
of
the operation loaded a zero into the accumulator. Otherwise it
is
reset.
3)
Sign Flag (S) - This
flag
is
intended to be used with signed numbers and it
is
set
if
the result
of
the operation
was negative.
Since bit 7 (MSB) represents the sign
of
the number (A negative number has a 1 in bit 7), this
flag
stores the state
of
bit 7 in the accumulator.
4) Parity
/Overflow Flag (P /V) - This dual purpose
flag
indicates the parity
of
the result in the accumulator when
logical operations are performed (such
as
AND A,
B)
and it represents overflow when signed two's comple-
ment arithmetic operations are performed. The Z-80A overflow flag indicates that the two's complement num-
ber in the accumulator
is
in error since it has exceeded the maximum possible (+127) or
is
less
than
the mini-
mum possible (
-128)
number than can be represented in two's complement notation. For example consider
adding:
+120 011 I 1000
+105 0110 1001
C 0 1110 0001 =
-31
(wrong) Overflow has occurred
Here the result
is
incorrect. Overflow has occurred and yet there
is
no carry
to
indicate an error.
For
this case
the overflow
flag
would be set. Also consider the addition
of
two negative numbers:
-5
=
-16
=
c =
11111011
1111 0000
11101011
=
-21
correct
Notice that the answer
is
correct
but
the carry
is
set
so
that this
flag
can not be used
as
an overflow indicator.
In this case the overflow would
not
be set.
For logical operations (AND,
OR, XOR) this flag
is
set
if
the parity
of
the result
is
even and it
is
reset if it
is
odd.
There are also two non-testable bits in the flag register. Both
of
these are used for
BCD
arithmetic. They are:
1) Half carry
(H) - This
is
the
BCD
carry or borrow result from the least significant four bits
of
operation. When
using the DAA (Decimal Adjust Instruction) this flag
is
used
to
correct the result
of
a previous packed decimal
add or subtract.
2) Add/Subtract Flag (N) -
Since the algorithm for correcting
BCD
operations
is
different for addition or sub-
traction, this flag
is
used
to
specify what type
of
instruction was executed last so that the DAA operation will
be correct for either addition or subtraction.
The Flag register can be accessed by the programmer and its format
is
as
follows:
I s I z I X I H I X I
P/V
N I c I
X means
flag
is
indeterminate.
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