111
3.0 PIN DESCRIPTION
A diagram
of
the Z-80A-PIO pin configuration
is
shown in Figure 3 .0-1. This section describes the function
of
each
pin.
D
7
-D
0
Z-80A-CPU Data Bus (bidirectional, tristate)
This bus
is
used
to
transfer all data and commands between the Z-80A-CPU and the Z-80A-PIO. D
0
is
the
least significant bit
of
the bus.
B/ A Sel Port B or A Select (input, active high)
This pin defines which port will be accessed during a data transfer between the
Z-80A-CPU and the Z-80A-
PIO.
A low level
on
this pin selects Port A while a high level selects Port
B.
Often Address bit A
0
from the
CPU will be used for this selection function.
C/D Sel Control or Data Select (input, active high)
This pin defines the type
of
data transfer
to
be performed between the CPU and the PIO. A high level on this
pin during a
CPU write
to
the PIO causes the Z-80A data bus
to
be interpreted
as
a command for the port
selected by the B/ A Select line. A low level
on
this pin means
that
the Z-80A data bus
is
being used to trans-
fer data between the CPU and the PIO. Often Address bit A
1
from the
CPU
will be used for this function.
CE
Chip Enable (input, active low)
A low level on this pin enables the
PIO to accept command or data inputs from the CPU during a write cycle
or
to
transmit data
to
the CPU during a read cycle. This signal
is
generally a decode
of
four
1/0
port numbers
that encompass port A and
B,
data and control.
4
MHz
System Clock (input)
The
Z-80A-PIO uses the standard
Z-SOA
system clock to synchronize certain signals internally. This
is
a
single phase clock.
M1
Machine Cycle One Signal from CPU (input, active low)
IORQ
RD
This signal from the
CPU
is
used
as
a sync pulse to control several internal PIO operations. When M I
is
active
and the RD signal
is
active, the Z-80A-CPU
is
fetching an instruction from memory. Conversely, when M 1
is
active and IORQ
is
active, the CPU
is
acknowledging
an
interrupt. In addition, the
M1
signal has two other
functions within the
Z-SOA-PIO.
1.
M 1 synchronizes the PIO interrupt logic.
2. When
M1
occurs without an active RD or IORQ signal the PIO logic enters a reset state.
Input/Output
Request from Z-80A-CPU (input, active low)
The
IORQ signal
is
used in conjunction with the B/A Select, C/D Select, CE, and RD signals
to
transfer com-
mands and data between the Z-80A-CPU and the Z-80A-PIO. When CE, RD and IORQ
are
active, the port
addressed by B/A will transfer data
to
the CPU
(a
read operation). Converse!:,',
whenCE
and IORQ are active
but
RD
is
not active, then the port addressed by B/ A will be written into from the
CPU
with either data or
control information
as
specified by the C/D Select signal. Also,
if
IORQ and M 1 are active simultaneously,
the
CPU
is
acknowledging an interrupt and the interrupting
port
will automatically
plac~
its interrupt vector
on
the CPU data bus if it
is
the highest priority device requesting an interrupt.
Read
Cycle Status from the Z-80A-CPU (input, active low)
If
RD
is
active a MEMORY READ or 1/0 READ operation
is
in progress. The RD signal
is
used with B/A
Select,
C/D Select,
CE
, and IORQ signals
to
transfer data from the Z-80A-PIO to the
Z-SOA-CPU.
To Next Page
Loading...
