118
5.3
BIDIRECTIONAL
MODE (MODE 2)
This mode
is
merely a combination
of
Mode 0 and Mode 1 using all four handshake lines. Since it requires all four
lines, it
is
available only
on
Port A. When this mode
is
used
on
Port
A, Port B must be set
to
the Bit Control Mode. The
same interrupt vector will be returned for a Mode 3 interrupt
on
Port
B and an
input
transfer interrupt during Mode 2
operation
of
Port
A. Ambiguity
is
avoided
if
Port B
is
operated in a polled mode and the
Port
B mask register
is
set
to
inhibit all bits.
Figure
5.0-3 illustrates the timing for this mode.
It
is
almost identical
to
that
previously described for Mode 0 and
Mode 1
with
the Port A handshake lines used for
output
control and the
Port
B lines used for input control. The differ-
ence between the two modes is that, in Mode 2, data is allowed
out
onto
the bus only when the A strobe
is
low. The
rising edge
of
this strobe can be used
to
latch the data into the peripheral since the data will remain stable until after
this edge. The input portion
of
Mode 2 operates identically
to
Mode 1. Note
that
both
Port
A and
Port
B must have
their interrupts enabled
to
achieve an interrupt driven bidirectional transfer.
<I>
A ROY
A
STB
B ROY
WR
~
RD
·
CE
·C/
D
·
IORQ
FIGURE
5.0
-3
PORT
A,
MODE
2
{BIDIRECTIONAL)
TIMING
The peripheral must
not
gate data
onto
a
port
data bus while A STB
is
active. Bus contention
is
avoided
if
the peri-
pheral uses B STB
to
gate
input
data onto the bus. The PIO uses the B STB low level
to
latch this data. The PIO has
been designed with a zero hold time requirement for the data when latching in this mode
so
that
this simple gating
structure can be used
by
the peripheral. That is, the data can be disabled from the bus immediately after the strobe
rising edge.
5.4 CONTROL MODE (MODE 3)
The control mode does
not
utilize the handshake signals and a normal
port
write or
port
read can be executed at
any time. When writing, the data will be latched into
output
registers with the same timing as Mode 0. A RDY will be
forced low whenever Port A
is
operated
in
Mode 3. B RDY will be held low whenever
Port
B
is
operated in Mode 3
unless Port A
is
in Mode 2. In the latter case, the state
of
B RDY will
not
be affected.
When reading the PIO, the data returned
to
the CPU will be composed
of
output
register data from those
port
data
lines assigned
as
outputs
and input register data from those
port
data lines assigned
as
inputs. The
input
register will
contain data which was present immediately prior
to
the falling edge
of
RD. See Figure 5
.04
.
Rb
·
DO
·
DI
~)---------
Ti
mi
ng
D
iagra
m R
efers
to Bit M ode Read L
DATA
WORD I
PLACED
ON
BUS
FIGURE
5.0-4
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