Siemens SIPART DR24 - Page 264

9 List of Abbreviations Manual
262
SIP ART DR24 6DR2410
C79000-G7476-C153-03
CLb* Digital output 1 to 8 of the clock
CLCY Parameter: Number of cycles of the programs (Cloc)
CLFo Parameter: Clock format (Cloc)
CLoc Clock (d)
CLPA Paramterization preselection mode: Clock parameter
CLPr Parameter: Number of intervals (Cloc)
CLSb Parameter: Fast clock (Cloc)
CLti Parameter: Interval time (Cloc)
CMPL Longitudinal parity formation Lrc complement
CMPt -- Err Compatibility error between customer program and operating software
Cnt Demultiplexer
CoMP Comparator (b)
CoUn Counter (b)
CP K
p
, Proportional action factor (controller)
CPt* Correction computer 1, 2 (c)
CPU.-Err Error message CPU (Slave Processor)
CPU-Err Error message CPU
CSE* S-controller 1, 2; external position feedback signal (h)
CSi* S-controller 1, 2; internal position feedback signal (h)
CYCL cyclic
d0*.F Arithmetic block d01 to d03, function assignment
d**.* Arithmetic block d1 to d3, input 01 to 12 (sink)
d*.*A Arithmetic block d1 to d3, output 1 to 9 (source)
d*.**. Arithmetic block d1 to d3, output 10 to 14 (source)
dA Parameter, Start (display range)
dA--L Display selection, analog display LEDs (hdEF)
dA* Analog display 1, 2
dA*.* Analog display 1, 2; Input 1, 2 (sink)
dA*.U Analog display 1, 2; switching (sink)
dd* Digital display 1, 2, 3
dd*.* Digital display 1 to 3; Input 1, 2 (sink)
dd*.U Digital display 1 to 3, switching (sink)
dE Parameter, End (display range)
dEbA Response threshold (dead band) (b)
dEF define
dELt delete
dFF D flip--flop (b)
diF Differentiator (b)
div Divider (b)
dP Decimal point (display dd1 to dd3)
dPon Flashing of dd1 to dd3 after Pon (hdEF)
dPv Parameter: Adaptation step direction
dr Repetition rate (displays)
dti* Dead time element 1, 2 (dead-time) (c)
dY Parameter: Adaptation step height
Eor Exor (b)
Err Error