Figure 4.8. Transmit FIFO Write
If the host MCU needs to read the receive FIFO, it has to pull the NSEL pin low and send the 0x77 Receive FIFO Read command ID.
The MCU should provide as many clock pulses on the SCLK pin as necessary for the radio to clock out the requested amount of bytes
from the FIFO on the SDO pin. Finally, the host MCU should pull up the NSEL pin.
Figure 4.9. Receive FIFO Read
If more than 64 bytes are written into the Transmit FIFO, then a FIFO overflow occurs. If more bytes are read from the Receive FIFO
than it holds, then FIFO underflow occurs. In either of these cases, the FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt flag will
be set. The radio can also generate an interrupt on the NIRQ pin if this flag is enabled. The interrupt flag has to be read, issuing a
GET_CHIP_STATUS or GET_INTERRUPT_STATUS command, to clear the pending interrupt and release the NIRQ pin.
AN954: Programming Guide for EFM8 and EZRadio ®
Application Programming Interface
silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 21
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