Skyworks Si5391 - Dividers

3.1 Dividers
There are five main divider classes within the Si5391/Si5391P shown above in the Figure 3.1 Si5391 Block Diagram on page 8.
1. Wide range input dividers Pfb, P2, P1, P0
• Only integer divider values
• Range is from 1 to 2
16
– 1
• Since the input to the phase detector needs to be > 10 MHz, the practical range is limited to ~75 on the high side.
• Each divider has an update bit that must be written to cause a newly written divider value to take effect.
2. Narrow range input divider Pxaxb
• Only divides by 1, 2, 4, 8
3. Feedback M divider
• Ultra low jitter in fractional and integer modes
• MultiSynth divider
• Integer or fractional divide values
• 44 bit numerator, 32 bit denominator
• Practical range limited by phase detector range of 10–120 MHz and VCO range of 13500–14256 MHz
• This divider has an update bit that must be written to cause a newly written divider value to take effect.
4. Output N dividers
• Ultra low jitter in fractional and integer modes
• MultiSynth divider
• Integer or fractional divide values
• 44 bit numerator, 32 bit denominator
• Min value is 10
• Maximum value is 2
12
– 1
• Each N divider has an update bit that must be written to cause a newly written divider value to take effect. In addition there is a
global update bit that when written updates all N dividers.
5. Output R divider
• Only even integer divide values
• Min value is 2
• Maximum value is 2
25
– 2
Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 10. Digitally-Controlled Oscillator
(DCO) Mode (All Si5391 Devices Except Si5391P) for more information and block diagrams on DCO mode.
Si5391 Reference Manual • Functional Description
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