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Describes field programming using ClockBuilder Pro for Si5391/Si5391P devices.
Details restrictions and requirements for the Si5391P Precision grade for <100 fs jitter.
Outlines rules for output clock placement and format for Si5391P <100 fs jitter.
Explains the five main divider classes (input, feedback, output N, output R) in the Si5391/Si5391P.
Describes changing output frequencies dynamically without altering PLL settings.
Explains dynamic frequency changes with PLL settings using CBPro register maps.
Explains how to select clock inputs using pins or register control.
Details various input types supported by the Si5391, including crystal and external clocks.
Describes fault indicators like Loss of Signal (LOS) and Loss of Lock (LOL).
Explains how the crosspoint switch connects MultiSynths to output drivers.
Details the synchronization of output R dividers for phase alignment.
Provides guidelines for output clock placement to minimize crosstalk and jitter.
Covers differential and LVCMOS output signal formats and their configurations.
Explains how clock outputs are enabled or disabled using various signals.
Specifies settings for output buffer supply voltage to match VDDOx.
Describes how to adjust input-to-output skew dynamically.
Details controlling N dividers digitally for frequency margining or CPU speed control.
Explains using the M divider to treat the VCO as a DCO for frequency changes.
Describes the I2C serial interface operation, addressing, and modes.
Details the SPI serial interface operation, including 4-wire and 3-wire modes.
Provides layout guidelines for the 64-pin QFN package, including layer descriptions.
Details registers for powering down unused functions to minimize power consumption.
Offers recommendations for power supply filtering and layout for optimal timing performance.
Explains the four classes of supply voltages and requirements for output clock alignment.
Provides guidelines for using grounding vias for heat transfer and minimizing inductance.
Differentiates between base and factory preprogrammed (custom OPN) Si5391/Si5391P devices.
Describes base devices and their configuration requirements for usable operation.
Explains factory preprogrammed devices and custom OPN creation using ClockBuilder Pro.
Provides an overview of the register map structure and default settings.
Details registers on Page 0, including Die Revision, Page Select, and Part Number.
Details registers on Page 1, covering output clock configuration and divider settings.
Details registers on Page 2, focusing on P-dividers and their enable/set controls.
Details registers on Page 3, covering N-divider numerator, denominator, and update bits.
Details registers on Page 9, including XAXB configuration and I/O voltage select.
Details registers on Page A, covering N divider clocks, phase interpolator bypass, and power down.
Details registers on Page B, including loss of signal clock disable and divider clock disables.
General| Brand | Skyworks |
|---|---|
| Model | Si5391 |
| Category | Portable Generator |
| Language | English |
