N3 dynamic phase adjust works the same as N0 dynamic phase adjust (0xA38).
Table 15.98. 0x0A44 N3 Dynamic Phase Adjust Step Size
Reg Address Bit Field Type Name Description
0x0A44 7:0 R/W N3_PHASE_STEP N3 step size from 1 to 255 in units of Tvco, the VCO
period.
Table 15.99. 0x0A45 N3 Dynamic Phase Adjust Step Size Count
Reg Address Bit Field Type Name Description
0x0A45 7:0 R/W N3_PHASE_COUNT Lower byte of number of N3 step size changes.
0x0A46 15:8 R/W N3_PHASE_COUNT Upper byte of number of N3 step size changes.
Table 15.100. 0x0A47 N3 Dynamic Phase Adjust Command
Reg Address Bit Field Type Name Description
0x0A47 0 R/W N3_PHASE_INC Writing a 1 initiates a phase increment.
0x0A47 1 R/W N3_PHASE_DEC Writing a 1 initiates a phase decrement.
N4 dynamic phase adjust works the same as N0 dynamic phase adjust (0xA38).
Table 15.101. 0x0A48 N4 Dynamic Phase Adjust Step Size
Reg Address Bit Field Type Name Description
0x0A48 7:0 R/W N4_PHASE_STEP N4 step size from 1 to 255 in units of Tvco, the VCO
period.
Table 15.102. 0x0A49 N4 Dynamic Phase Adjust Step Size Count
Reg Address Bit Field Type Name Description
0x0A49 7:0 R/W N4_PHASE_COUNT Lower byte of number of N4 step size changes.
0x0A4A 15:8 R/W N4_PHASE_COUNT Upper byte of number of N4 step size changes.
Table 15.103. 0x0AB N4 Dynamic Phase Adjust Command
Reg Address Bit Field Type Name Description
0x0A4B 0 R/W N4_PHASE_INC Writing a 1 initiates a phase increment.
0x0A4B 1 R/W N4_PHASE_DEC Writing a 1 initiates a phase decrement.
15.7 Page B Registers Si5391
Table 15.104. 0x0B2E Synchronous Output Disable Timeout Value
Reg Address Bit Field Type Name Description
0x0B2E 6:0 R/W MS_OD_G_TIMEOUT Controls the synchronous output disable timeout value
during a hard reset.
0x0B2E 7 R/W MS_OD_G_TIMEOUT_EN
Si5391 Reference Manual • Si5391A/B Register Map
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