RDR-GX210
3) VIDEO INPUT / RECORD PATH
MPEG
Encoder
CS92686
IC201
VIDEO
DECODER
TVP5146
IC501
14.31818MHz
1394 PHY
TSB41AB1
IC401
1394 PHY
TSB41AB1
IC401
‘L’
SYSCLK
I2C Control
24.576MHz
PCNT[1:0]
DVCLK
PD[7:0]
TPA+/-
TPB+/-
R.656 Data From A.Video IN
R.656 Data From DV1394 IN
27MHz: A.Video In
27MHz: DV1394 IN
I2C Control
ANALOG VIDEO EE / REC DV1394 EE / REC
High
Impedance
state
MPEG
Encoder
CS92686
IC201
27MHz
VIDEO
DECODER
TVP5146
IC501
14.31818MHz
p
u
^
a
W
TU_V_IN
}
p
u
j
s
r
‘H’
SYSCLK
CS982_CLK
I2C Control
I2C Control
I2C Control
High
Impedance
state
ITU-R.BT656 format : 8Bit Data & Data Clock
3-state-buffer is disabled and buffer output is High-Z state.
VIN_CLK (Data Clock:27MHz) is generated from TVP5146.
ITU-R.BT656 format : 8Bit Data & Data Clock
TVP5146 Clock Output is High-Z State by IIC control.
3-state-buffer is Enabled by enable pin “Low” state
VIN_CLK (Data Clock:27MHz) is generated from IC503.
10
98
MPEG
DECODER
CS98200
IC301
^[oj|W[
pj\WZ
^[oj|W[
pj\WZ
27MHz
CS982_CLK
I2C Control
pj\WZ
^[sjXY\
10
98
p
u
^
a
W
}
p
u
j
s
r
V1_ IN
75ȍ
V2_ IN
75ȍ
Y_ IN
75ȍ
C_ IN
75ȍ
100Kȍ
TUNER
TUNER
RF SIGNAL
1
7
8
17
80
40
43,44,45,46
47,50,51,52
^[oj|W[
pj\WZ
^[oj|W[
pj\WZ
MPEG
DECODER
CS98200
IC301
40
57,58,59,60
102,103,104,106
131
7,75
73
63,64,65,66
67,70,71,72
7,75
73
63,64,65,66
67,70,71,72
131
57,58,59,60
102,103,104,106
183
pj\WZ
^[sjXY\
183
DV_PASSn
DV_PASSn
3-5 3-6
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9
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8
9
4
2
9
8
T
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L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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