56
SCD-XB770
Pin No. Pin Name I/O Description
45 AVSS0 —
Ground terminal (analog system)
46 IGEN I
Stabilized current input for operational amplifiers
47 AVDD0 —
Power supply terminal (+3.3V) (analog system)
48 ASYO O
EFM full-swing output terminal
49 ASYI I
Asymmetry comparator voltage input terminal
50 RFAC I
EFM signal input from the CXD1881R (IC001)
51 AVSS1 —
Ground terminal (analog system)
52 CLTV I
Internal VCO control voltage input
53 FILO O
Filter output for master PLL
54 FILI I
Filter input for master PLL
55 PCO O
Charge pump output for master PLL
56 AVDD1 —
Power supply terminal (+3.3V) (analog system)
57 BIAS I
Asymmetry circuit constant current input terminal
58 VCTL I
VCO control voltage input terminal for the wideband EFM PLL Not used (fixed at “L”)
59 V16M O
VCO oscillation output terminal for the wideband EFM PLL Not used (open)
60 VPCO O
Charge pump output terminal for the wideband EFM PLL Not used (pull down)
61 DVDD2 —
Power supply terminal (+3.3V) (digital system)
62 ASYE I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on
Not used (fixed at “H”)
63 MD2 I
Digital out on/off control signal input from the CPU (IC901)
“L”: digital out off, “H”: digital out on
64 DOUT O
Digital audio signal output to the DIGITAL (CD) OUT OPTICAL (IC309)
65 LRCK O
L/R sampling clock signal (44.1 kHz) output to the CXD1882R (IC701) and CXD9647R (IC803)
66 PCMD O
Serial data output to the CXD1882R (IC701) and CXD9647R (IC803)
67 BCLK O
Bit clock signal (2.8224 MHz) output to the CXD1882R (IC701) and CXD9647R (IC803)
68 EMPH O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used (open)
69 XTSL I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “H” in this set)
70 DVSS2 —
Ground terminal (digital system)
71 XTAI I
System clock input terminal (33.8688 MHz)
72 XTAO O
System clock output terminal (33.8688 MHz) Not used (open)
73 SOUT O
Serial data output terminal Not used (open)
74 SOCK O
Serial data reading clock signal output terminal Not used (open)
75 XOLT O
Serial data latch pulse signal output terminal Not used (open)
76 SQSO O
Subcode Q data output to the CPU (IC901)
77 SQCK I
Subcode Q data reading clock signal input from the CPU (IC901)
78 SCSY I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used (open)
79 SBSO O
Subcode serial data output to the CXD1882R (IC701)
80 EXCK I
Subcode serial data reading clock signal input to the CXD1882R (IC701)
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