Chapter 5: UEFI BIOS (for EPYC 7002 Series)
103
Memory Interleaving
This setting controls fabric level memory interleaving. Note that the channel, die and socket
have requirements on memory populations and it will be ignored if the memory doesn't
support the selected option. The options are Disabled and Auto.
Memory Interleaving Size
This setting controls the memory interleaving size. This determines the starting address of
the interleave (bit 8, 9, 10 or 11). The options are 256 Bytes, 512 Bytes, 1 KB, 2 KB or Auto.
Chipset Interleaving
This setting controls interleave memory blocks across the DRAM chip for node 0. The
options are Disabled and Auto.
BankGroupSwap
This setting controls the Bank Group Swap. The options are Enabled, Disabled and Auto.
CPU1 Memory Information
These sections are for informational purposes. They will display some details about the
detected memory according to each CPU on the motherboard, such as:
• Detected Size (per slot, in MB)
• Current Speed (MT/s)
PCIe/PCI/PnP Conguration
This menu provides PCIe/PCI/PnP conguration settings and information.
PCI Bus Driver Version
Above 4G Decoding
This setting Enables or Disables 64-bit capable devices ability to be decoded in above 4G
address space (only if the system supports 64-bit PCI decoding).
SR-IOV Support
If the system has SR-IOV capable PCI-E devices, this setting will Enable or Disable the
Single Root IO Virtualization Support for the system.
BME DMA Mitigatioin
Use this setting to re-enable the Bus Master Attribute that was disabled during PCI enumeration
for PCI bridges after SMM is locked. The options are Enabled and Disabled.
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