45
Chapter 2: Installation
SGPIO Headers
I-SGPIO1 and I-SGPIO2 (Serial General Purpose Input/Output) headers are used to
communicate with the enclosure management chip on the backplane.
SGPIO Header
Pin Denitions
Pin# Denition Pin# Denition
1 NC 2 NC
3 Ground 4 DATA Out
5 Load 6 Ground
7 Clock 8 NC
NC = No Connection
Disk-On-Module Power Connector
The Disk-On-Module (DOM) power connectors at JSD1 and JSD2 provide 5V power to a
solid-state DOM storage device connected to one of the SATA ports. See the table below for
pin denitions.
DOM Power
Pin Denitions
Pin# Denition
1 5V
2 Ground
3 Ground
DESIGNED IN USA
X11SSH-TF
REV:1.01
BAR CODE
SAS CODE
MEGERAC
LICENSE
IPMI CODE
MAC CODE
PRESS FIT
Intel
PCH
LSI3008
(-CTF only)
X550
BT1
JSAS1
JSTBY1
LEDS1
J2
SP1
LE1
LEDBMC
LEDPWR
JPSAS1
JOH1
JL1
JPG1
JBR1
JVRM2
JVRM1
JPME2
JVR1
JPS1
JPB1
JI2C1
JI2C2
JWD1
JPTG1
JSD2
JSD1
FAN5
FANA
FAN3
FAN4
FAN1
FAN2
JUIDB1
JIPMB1
JPI2C1
JD1
JPWR2
I-SGPIO2
I-SGPIO1
I-SATA7
I-SATA6
I-SATA3
I-SATA2
I-SATA1
I-SATA0
JF1
JTPM1
JPWR1
I-SATA5
I-SATA4
MH8
J24
LE3
JBT1
JPCK1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
USB8(3.0)
USB4/5
USB9/10(3.0)
USB2/3
CPU Socket LGA1151
PCH SLOT4 PCI-E 3.0 X2 (IN X4)
CPU SLOT6 PCI-E 3.0 X8
VGA
LAN2
LAN1
USB6/7
(3.0)
USB0/1
IPMI_LAN
COM2
COM1
1 2
3
4
1. I-SGPIO1
2. I-SGPIO2
3. JSD1
4. JSD2
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