Supermicro X12SPZ-SPLN6F - Page 78

Super X12SPZ-SPLN6F/LN4F User's Manual
78
Adjacent Cache Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Enable and Disable.
DCU Streamer Prefetcher (Available when supported by the CPU)
Select Enable to enable the DCU (Data Cache Unit) Streamer Prefetcher which will stream
and prefetch data and send it to the Level 1 data cache to improve data processing and
system performance. The options are Disable and Enable.
DCU IP Prefetcher (Available when supported by the CPU)
Select Enable for DCU (Data Cache Unit) IP Prefetcher support, which will prefetch IP
addresses to improve network connectivity and system performance. The options are Enable
and Disable.
LLC Prefetch
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L3 cache to improve CPU performance. The options are Disable
and Enable.
Extended APIC
Select Enable to activate APIC (Advanced Programmable Interrupt Controller) support. The
options are Disable and Enable.
VMX
Use this feature to enable or disable Vanderpool Technology. The options are Disable and
Enable.
Enable SMX
Use this feature to enable or disable Safer Mode Extensions. The options are Disable and
Enable.
PPIN Control
Select Unlock/Enable to use the Protected Processor Inventory Number (PPIN) in the system.
The options are Unlock/Disable and Unlock/Enable.
AES-NI
Select Enable to use the Intel Advanced Encryption Standard (AES) New Instructions (NI) to
ensure data security. The options are Disable and Enable.