Synopsys, Inc. 35
SolvNetPlus
DesignWare
5.60a
March 2020
PCIe IP Prototyping Kit Installation Guide Setting Up Software Environment
DW_axi 4.02a The DW_axi component is a multilayer interconnect implementation of the AXI
protocol, which is designed for high-performance, high-frequency system
designs.
DW_axi_x2x 1.06a The DW_axi_x2x is a configurable bridge between an AXI master and an AXI
slave with any combination of different data port widths, different clock
frequencies, and different endianness.
DW_axi_gm 2.03a The DW_axi_gm is a configurable module between a generic interface (GIF)
and an AXI bus.
DW_axi_gs 2.02a The DW_axi_gs is used to reply to requests from the PCIe Axi bridge.
Verification IP (VIP)
svt P-2019.09 VIP testbenches that comply with the SystemVerilog Universal Verification
Methodology (UVM).
a. Make sure to install all packages of HAPS ProtoCompiler (ConfPro and ProtoCompiler Runtime)
Table 2-1 Licensing and Tools Requirements (Continued)
License/Tool Version Description
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