Synopsys DesignWare 826-0 - Page 53

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SolvNetPlus
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5.60a
March 2020
PCIe IP Prototyping Kit Installation Guide Status LEDs
The AXC002 CPU Card features two seven-segment displays, which are controlled by a field of the SWPORTB_DR register as listed in Table A-4.
Table A-4 Control Bits of the Seven-Segment Displays
Control Bit Description
SWPORTB_DR[23:16] Controls the upper seven-segment display. A segment of the display is ON
when its control bit is set to 1.
SWPORTB_DR[31:24] Controls the lower seven-segment display. A segment of the display is ON
when its control bit is set to 1.
SWPORTB_DR[16]
SWPORTB_DR[21]
SWPORTB_DR[22]
SWPORTB_DR[20]
SWPORTB_DR[17]
SWPORTB_DR[23]
SWPORTB_DR[18]
SWPORTB_DR[19]
SWPORTB_DR[24]
SWPORTB_DR[29]
SWPORTB_DR[30]
SWPORTB_DR[28]
SWPORTB_DR[25]
SWPORTB_DR[26]
SWPORTB_DR[27]
SWPORTB_DR[31]