Tektronix FG 5010 User Manual

Theory
of
Operation
-
FG 5010
Differential
pair
Q1230A -
Q1230B drive
Q1230D and
Q1230C in cascode , respectively . The cascode configura
tion
reduces the
potential for
thermal
mismatch
between
Q1230A and B. This effect is especially pronounced at very
low
frequencies
. Since the
emitter
of each
cascode
transis
tor remains at about +3.5 V , neither collector of the driving
pair remains very far apart in voltage . To further equalize
power
consumption
, C1222
-
R1226
and C1230
- R1234
are
compensation
networks
that
match the collector
to
emitter
impedances . The net result of the arrangement is that while
the current through one transistor increases and its voltage
decreases , the opposite is true for the other , and the power
dissipated
remains relatively
constant .
From the
collectors
of the cascode
pair , the output
signal
is fed to Q1340A and B , another differential amplifier . These
two transistors are also packaged together to reduce ther
mal differences . Q1330A and B form a current mirror , in that
the
current through
Q1340A
is
reflected
back to
the collec
tor of Q1340B . By using the mirror circuit as a load , the gain
is doubled at the output of the stage . Diodes CR1321 and
CR1320 provide first - order thermal compensation for the
quiescent
operating point of
the output stage
, and
VR1340
equalizes
the
power dissipation
in
Q1340A and
Q1340B
to
reduce thermal distortion .
The output stage consists of transistors Q1321 and
Q1320 , plus related components . The transistors are biased
to operate class AB , in that both are conducting during
small
- signal
excursions , but only
one or the other
conducts
when large signals are amplified . The two output transistors
are mounted in a way to share a common heat conductor to
equalize the temperature of the devices . Partial compensa
tion for any differential heating of the output pair comes
from R1340 , which applies negative feedback to the base of
Q1340B . Zener diodes VR1221 and VR1220 further reduce
power dissipation in the output pair by reducing the V
to
about 4 V on each transistor . From the junction of the two
transistors , the amplified sine wave is applied to the Func
tion Selector depicted on Diagram 20. From there , the sine
wave is applied to the Multiplier circuits in the Output
Section .
CE
22
4-30
SQUAREWAVE BUFFER AND
TRIGGER INTERFACES
Introduction
The circuits depicted on Diagram 22 include the Square
wave Buffer , which receives the buffered ECL signals from
Loop 1 , and generates a +1 V to – 1 V squarewave signal
for application to the Function Selectors depicted on Dia
gram 20. The Trigger Interfaces circuit receives the buffered
ECL signals from Loop 1 , and generates the TRIGGER OUT
and TRIGGER COMPL OUT signal . The N Burst Interface
receives the ECL signal from Loop 1 and modifies it to
produce
the
clock that is
applied
to the
N
Burst circuits
.
Trigger
Interfaces
The
Trigger Interfaces
consists
of line
receivers
U1200A
and U1200C , transistors Q1201 and Q1200 , plus related
circuitry . The circuit isolates the squarewave signal from
Loop
1 and
applies it
to the
Squarewave
Buffer
and
the
TRIGGER OUT connection .
The SELECTED SQWV and SELECTED SQWV signals
are
applied to pins
4 and 5 ,
respectively , of U1200A
, and to
the base of Q1102 and Q1101 . Direct connection to this
stage was made to avoid the propagation delay that would
occur
through the line
receivers
,
since this
circuit drives the
Burst
Circuits
.
N Burst Interface
Transistors Q1102 , Q1101 , and Q1100 operate in con
junction to
produce
a TTL -
level signal for the
N Burst
circuit .
As the applied SELECTED SQWV signal at the base of
Q1101 moves negative to turn the transistor on , the input to
Q1102 moves positive to cut off the transistor . Current
through Q1101 and R1002 produce the positive excursion
of the output . When the polarity of both drive signals re
verse
,
Q1101 cuts off ,
Q1102
conducts , and
Q1100 con
ducts
to pull the
output to
ground .
Schottky barrier diode
CR1100
prevents
Q1100 from
saturating ,
which
would slow
the rising edge of the output signal .
Trigger
Interface
The
two
squarewave
signals (
SELECTED
SQWV
and
SELECTED SQWV
) are also
connected to
line
receiver
U1200A , which isolates the Loop 1 Selected Squares ECL
Driver from the other loads . From U1200A , the signals are
applied to line receivers U1200B ( which drives the Square
wave Buffer ) and U1200C ( which drives the Trigger Inter
faces
circuits ) .
Line receiver U1200C applies the buffered squarewave
signals and
its complement
to
Q1200 and
Q1201 . This
am
plifier
is driven
on each side
from cutoff
to
saturation . Resis
tor R1202 reduces circuit gain during the switching time ,
when both transistors are conducting . From the collector of
Q1200
, the
squarewave signal
is applied
to J1200 , the
TRIGGER COMPL OUT jack . From the collector of Q1201 ,
the signal is connected to J1201 . Both outputs are terminat
ed into a 50 2 load . Connector P1201 can be connected to
either J1200 or J1201 to provide a complemented or normal
signal
output . The
signal that passes
through P1015
- J1015 ,
complemented
or
normal , is
eventually fed out
the TRIG
OUTPUT
jack
on the front
panel .
U
U
U
U
U
U
نال
U
U
U
C
»
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English