Tektronix FG 5010 User Manual

Theory
of
Operation -
FG
5010
CPU SECTION
The
Processor Board
contains the
Microprocessor and its
associated clock circuit , the instrument RAM and ROM
storage facilities , and the various input / output and bus cir
cuits and with other FG 5010 circuit groups . The CPU Block
Diagram shows the relationship of the Processor Board cir
cuits ( the schematic diagrams for these circuits are shown
on Diagrams 5 through 9 ) and is included in the diagrams
section
of this
manual
.
Refer
to
that
block diagram for
sup
port of the following brief description .
At the center of FG 5010 functions is the Micro
processor , which controls all program - influenced oper
ations
.
It is
a
standard eight - bit
integrated
circuit
microprocessor . An associated 4 MHz oscillator provides
the clock for the
Processor
Board
circuits .
Communications
between the Microprocessor and other Processor Board cir
cuits is via an eight - bit parallel data bus ; selection of the
memory and input / output circuits is via a 16 - bit parallel ad
dress bus . Input / output circuits include the GPIB Interface ,
the
Versatile
Interface
Adapter , and
the
Keyboard
Display
Interface . Memory circuits include both RAM and ROM . In
addition , a
service
interconnect port
provides
for
connection
of a
test fixture to
aid in
maintenance
operations .
The GPIB
Interface
logic
provides
the
interface
between
the
Processor Board data
bus and the
external
IEEE
- 488
data bus that allows communications between the FG 5010
and other
instruments
and
controllers
.
Also , the GPIB
Inter
face
logic
handles
the
required
handshake
and
bus manage
ment
signals
.
The
Versatile
Interface Adapter
logic
performs
parallel
to - serial and serial - to - parallel conversion of data for trans
mission
between
the
Processor
Board
data bus and
the
FG 5010
Output Amplifier , Loop 1 ,
Loop 2 , and
Sine
Shaper
circuit groups ; and between the Loop 2 circuit group and the
Processor
Board
data
bus .
The
circuits
also
produce the
strobe signals to those circuit groups to effect such trans
fers . Closely associated with the Versatile Interface Adapter
is the Trigger Logic , which , under control of the Micro
processor
via
the port
logic ,
generates trigger / gate
signals
to
control
the
FG
5010
output .
The Keyboard / Display Interface operates under control
of the
Microprocessor to
generate
signals
that
display
infor
mation in the various front - panel indicators . Those indica
tors
include both
segmented
number
indicators
and
lights
which
are
operated in three
states
: on ,
blinking
, or
off .
Communications
between
these interface logic
circuits
and the Microprocessor is through a portion of the Proces
sor Board data bus that includes the Bidirectional Buffer .
4-48
Memory circuits include one kilobyte of external RAM ,
128 bytes of RAM internal to the Microprocessor , and 24
kilobytes of ROM for storage of FG 5010 operational data .
Note that the RAM circuits communicate with the Micro
processor
via the
Bidirectional
Buffer as
do the
interface
circuits .
The
Device Address
circuits
allow the user
to
select any
of the 31 valid IEEE - 488 bus addresses or the invalid ad
dress ( all five address switches set to 1 ) and which termina
tor is to be
used for bus
communication . An
internal
jumper
allows service
personnel
to
select normal ,
calibration
, or sig
nature analysis mode .
5 MICROPROCESSOR / 4 MHz CLOCK
Introduction
The
Processor Board diagram
contains
the
Micro
processor and 4 MHz Clock circuits . In addition , this con
tains part of the Service interconnect circuits and part of the
Read
/
Write
Control
Logic .
The Microprocessor circuit provides the detailed control
for all FG 5010
automatic
and
programmable
functions
. It is
a 6802 8 - bit microprocessor with an 8 - bit data bus and a
16 - bit
address bus . The
4- MHz clock
input to
the Micro
processor is provided by a crystal controlled oscillator that
is external to the microprocessor , rather than the internal
circuit , for a more precise and stable reference . This clock
signal is also used by other FG 5010 circuits .
Additional
circuits
on
diagram
5 are
the
control logic that
enables the read and write functions , and part of the service
interconnect
facilities
that
provide for
connection
of a test
fixture
.
4 MHz Clock
The 4
MHz
clock
circuit
consists
of a
Pierce
type
oscilla
tor ( basically a Colpitts oscillator with the voltage division
provided by base - to - emitter and collector - to - emitter capaci
tance ) , an
Emitter Follower
,
a
Differential
Amplifier
, and
sev
eral
Inverter -
Drivers
.
Transistor Q1131 and reference crystal Y1131 form the
basis for the oscillator . Crystal Y1131 is a 4 MHz anti - reso
nant mode device , and is connected across the base - collec
tor
junction of
Q1131
.
Feedback
capacitance is
provided by
the capacitor divider consisting of C1132 and C1134 . Ca
pacitors
C1132 and
C1134 are
chosen to
provide the
proper
parallel capacitance so that the crystal will operate at the
11
C
C
11
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D
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Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English