Tektronix FG 5010 User Manual

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design
frequency
of 4
MHz .
Resistor
R1134 acts as the
os
cillator
collector
load
;
capacitor
C1131
bypasses the
oscilla
tor
frequency .
The
rc
filter
consisting of
resistor
R1120
and
capacitor
C1122
filters
out
any
ripple
voltage
present on
the +5
V
supply as side effects of display currents . This rc network
stablizes the
amplitude of the
oscillator
circuit
. The
resistive
divider
consisting
of
R1131 and
R1132 sets the
bias on
the
oscillator
transistor .
Resistor
R1133
and
capacitor
C1133
stablize
the
operating
point .
Emitter
follower
transistor
Q1133
couples
the output sig
nal from the
oscillator
collector circuit . An
emitter follower
circuit
is
used so as
not to
excessively load
the
oscillator .
Resistor
R1135 provides
isolation
between the
oscillator
and Q1133 ; resistor R1136 is the load for Q1133 .
Transistors
Q1132
and
Q1231
form a
differential
amplifi
er that accepts
the emitter
follower
output
and
amplifies
it
appropriately to be used by following logic circuits . Capaci
tor C1135
couples the emitter
signal of
Q1133 to the base
circuit
of
Q1132
.
Both
Q1132
and
Q1231
are
biased by a
common resistor - diode network consisting of diode CR1231
and resistors R1231 , R1137 , R1233 and R1234 . The diode
produces
a
single diode drop
that is the
approximate equiv
alent of
the base -
emitter
drops
in
the two
transistors
,
Q1132 and
Q1231 . The
two
divider legs
then
provide
the
basis for the standing current in the transistors . The actual
value of the
standing
current
in the
differential pair is set
by
resistor
R1232
, the
common
emitter resistor .
From
emitter
follower
Q1133
,
the
signal is
applied
to
the
base of
Q1132 , which
switches
Q1132
on and
off at the
oscillator rate ,
shunting
current from
Q1231 periodically at
that rate .
At that
frequency
,
the base
of
Q1231 is
effectively
grounded through capacitor C1231 . The amplifier output
signal is developed across Q1231 collector resistor R1235 .
From
the
amplifier , the
output
signal
is
applied
to
invert
er -
driver
U1630F
,
which applies the 4
MHz
oscillator
signal
to the microprocessor pin 39 ( the EXTAL input ) , which is the
clock input
for the
microprocessor . The
U1630F output is
also
applied to GPIB
interface U1102
,
on
Diagram 7 , and to
parallel inverter - drivers U1630A and U1630B .
The
output from
these two
inverter
-
drivers
is
applied
through resistors R1630 and R1631 via connector P1050 ,
pin 7A to the
Loop 2 circuits ,
on
Diagram
1 ,
where it is used
as the
reference
clock
for the
frequency
control .
Capacitor
C1630
rounds the
signal
somewhat , by
removing
abrupt
transitions
, to
reduce the
noise that is
coupled
into
other
FG
5010
circuits
.
Theory
of
Operation
- FG
5010
Microprocessor
The
Microprocessor , U1310
,
contains
the
circuits
neces
sary to control the operation of the FG 5010. Since U1310 is
a
standard
6802
IC
and a
detailed
functional
description and
block
diagram is
provided in the
manufacturer's
documents ,
no
detailed
description is
provided
here
.
Only
a
description
of the
inputs
and
outputs is
provided
.
Bidirectional data
bus lines D0
through D7 are
connected
to Microprocessor pins 33 , 32 , 31 , 30 , 29 , 28 , 27 and 26
respectively . Note that not all of the opposite ends of the
signal paths connected to these pins are bidirectional in op
eration . Data are received from the ROM and address
switches on Diagram 9 , but are not transmitted to those
circuits . Data
are both
transmitted to and
received
from the
Bidirectional Buffer U1200
on
Diagram 7. The buffer ,
in turn ,
transmits to and receives from the GPIB Interface U1102
and the
RAM
U1400 and
U1500
,
both
on
Diagram 7 , and
the
Versatile
Interface Adapter U1720 , and
the Front
Panel
Interface U1830 , both on Diagram 8. Data are also transmit
ted to and
received from the
test
fixture that may
be con
nected to
J1220 , the service
interconnect
connector
. Note
that pin 26 of the Microprocessor is also connected to the
+5 V supply through resistor R1200 , which acts as a pull
up if the test fixture is not connected to the service
interconnect
.
Thus
,
if the
Microprocessor
attempts
to ac
cess the test fixture and the test fixture is not connected ,
the
returned high
will
indicate
to
the
microprocessor
that
this is
the
case .
Address
lines
A0 through
A15 are
supplied
from
microprocessor pins 9 through 20 and 22 through 25. These
lines are applied to the Address Decoders and Drivers on
Diagram
6 .
The
NMI input
,
connected to pin
6 of the
microprocessor ,
is not used inside the FG 5010. It is used only in the test
fixture that
connects to
J1220
.
The
Interrupt
Request
( IRQ ) line is also used by the test fixture , but is in addition
used by the
GPIB
Interface
logic
U1102
on
Diagram
7
and
the
Versatile
Interface
Adapter
logic
U1720
on
Diagram 8 .
IRQ can be
asserted
by
either U1102
or U1720 , and
causes
the Microprocessor to respond to the requesting interface
circuit .
Reset to the Microprocessor is applied as RESET ( active
low ) to pin 40 and is supplied from the Reset circuit on Dia
gram 4 via the Interconnect Board on Diagram 1 connector
P1010 , pin 11A and inverters U1610B and U1610C . After
the first
inversion
, by U1610B ,
the signal is
supplied
to the
Front Panel
Interface
U1830
on
Diagram 8. This signal
is
called LOGIC RESET and is active high . After the second
inversion , by U1610C , the signal is applied to the Micro
processor to the GPIB Interface Logic U1102 on Diagram 7 ,
4-49

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English