Tektronix FG 5010 User Manual

Theory of
Operation
-
FG
5010
and
to the
Peripheral
Interface logic
U1720
on
Diagram
8 as
the
LOGIC RESET
signal (
active low
) . It
initializes all of
these ICs
to the
power - on
condition
. It is
also
applied to
U1830 in the Front Panel Interface logic on Diagram 8 to
hold
off
display
signals . It
thus prevents the
front - panel indi
cators from blinking during reset operations .
The
Ram
Enable ( RE )
line
connected to pin
36 of the
Microprocessor is
ordinarily
high .
Placing
Forced
Instruction / Normal
jumper in the
Forced
Instruction
position
for
maintenance
operations causes
the RE input
to be low ,
disabling
the
microprocessor
internal
RAM .
This
signal is
also
applied to the
RAM address
selection
logic ( to
U1722A )
on
Diagram
7 and
to the
ROM
address
selection logic
( to
U1722D )
on
Diagram 9
as the
FI
signal . As with
the
Microprocessor
RAM
,
these
circuits are
disabled
under cer
tain conditions .
The
valid
memory
address
signal (
VMA )
indicates
to the
Field
Programmable Logic
Array on
Diagram 6 that
the
ROM address selected is valid and is not the partial result of
a 16 - bit calculation .
Read and write control signals are generated by the re
maining
circuits
on
Diagram
5 ,
under
control of
the R / W
signal from
pin 34 of
the
microprocessor and the
ROMDIS
(
ROM Disable )
signal from the
test
fixture via pin
10 of ser
vice interconnect connector J1220 . ( ROMDIS is normally
high
, but
is pulled
low
when the test
fixture
is connected
and
is supplying data . )
The R / W signal from the Microprocessor is applied di
rectly to
U1620A and
inverted
, by
U1510B , to
U1620C . The
ENABLE signal from the Microprocessor ( E , pin 37 ) is also
applied to
both
U1620A and
U1620C
as is
the
ROMDIS
signal
. The overall
effect is
that , when
ROMDIS is high
, the
ENABLE signal is high , the R / W line is high , the RD output
will
be low . When
ROMDIS
is high , R / W is
low , and enable
is high , the WR output will be low . Thus , only during EN
ABLE and only during an access cycle in which data are not
being
provided
by
the Test
Fixture
will RD or
WR be
low
.
(
Also , note that
the enable
signal is
supplied to the Test
Fixture (
J1220 ,
pin
2 ) .
These read / write control signals are applied to the GPIB
Interface logic
( U1102 ) on
Diagram 7 , the
Front Panel
Inter
face
U1830 on
Diagram 8 , the
Bidirectional
Buffer
U1200 on
Diagram 7 , and
the Versatile
Interface
Adapter logic U1720
on
Diagram
8 .
4-50
6
)
ADDRESS
DECODER
Introduction
Processor
Board
Diagram
6
contains
the Address
De
coder
circuits and
buffers
to
drive the
Processor
Board
ad
dress
lines .
The
Field
Programmable
Logic
Array (
FPLA )
examines all
addresses supplied by the Microprocessor , compares each
with a list of addresses in which data are to be changed ,
and
,
when such an
address
is detected
, causes
the
ROM in
which
that
address is
located to be
disabled and
new data
from
the
Patch
EPROM to be
substituted
. If the
address is
not
one in
which
data
is to be
changed
, the
Device
Address
Decoder
examines the
address lines
and
enables the select
ed
circuit (
such as ROM
, RAM
, GPIB
Interface , etc.
) . The
Address
Line Buffers
drive the address
lines and provide
for
disabling
certain
addresses for
substitution of
ROM
data .
Address Line
Buffers
The
Address
Line
Buffers consist
of tri - state
buffers
U1320 and U1312 , which provide the drive capacity to sup
ply
address
information
to all of the
addressable
circuits
on
the
Processor
Board . Integrated
circuit U1320 is the
buffer
for
the
lower three bits
and the
higher
five
bits of the
ad
dress
;
U1312 is the
buffer
for the
other eight
bits of
the
address . Note that since the inputs to the enable gate of
U1320 are
grounded ,
address bits
A0 , A1 , A2
, A11 , A12 ,
A13
, A14 ,
and A15 are
always
buffered and
applied
to the
addressable circuits . The enable gate for U1312 , however ,
is controlled by the FLAG output from Field Programmable
Logic
Array (
FPLA )
U1420
. If the
FLAG
signal is
low , the
gate
for
U1312
disables that
buffer ,
which removes the
A3
through A10
address bits
that were
supplied by
the Micro
processor
(
Diagram
5 ) .
Instead
,
address
information
from
the
FPLA is
substituted
on the bus
. The
outputs from buff
ers
U1320 and
U1312 are the
buffered
address bits BAO
through
BA15 .
Field Programmable Logic Array
Addresses in which
data are to
be
changed
are
detected
by
Field
Programmable
Logic
Array
(
FPLA )
U1420
.
Each
time
the
Microprocessor (
Diagram 5 )
supplies an
address
,
the
FPLA
compares
address bits A3
through A15
( which are
bits
10
through
112
inside the
FPLA )
with
the
list of
ROM
addresses that has
been
programmed into it . If the
address
matches one of
the addresses
on the list , the
FPLA causes
the
FLAG output
to become low
, which
disables
Address
Line
Buffer U1312 ,
disables
the
ROM in
which the
address
is
located (
Diagram
9 ) ,
and
enables the
Patch
EPROM
(
U1640 ,
also on
Diagram
9 ) . The
FPLA also
supplies
ad
dress
bits BA3
through
BA10
, an
address in the Patch
EPROM . At that address are new data to replace the data
at
the selected
ROM
address .
1
)
J
J
=
U
C
L
1
[
2
.
U
C
E
U
U

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English