Tektronix FG 5010

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This arrangement is used to provide for programming
flexibility . FPLA U1520 , Buffer U1312 , and Patch EPROM
U1640 ( Diagram 9 ) operate in concert to accomplish this . A
detailed description of the circuit operation follows .
In addition to the address inputs applied to input lines 10
through 112 , several other inputs control FPLA operations .
Input 113 from the Disable Patch / Normal jumper ( P1515 )
must be high for the FPLA to operate normally ; that is , in
the
NORMAL position
. If jumper
P1515 is in
the Disable
Patch position , the ROM circuits can be tested completely .
Input 114 is the Valid Memory Address ( VMA ) signal from
the
Microprocessor
(
Diagram 5 ) , which , when
high , indi
cates that the address selection is indeed valid from the
Microprocessor
. Input
115 is the
ROM Disable
(
ROMDIS )
signal
from service
interconnect
connector J1220
on Dia
gram 5 (
ROMDIS ) is
driven low
only by
the Test
Fixture that
can be connected to J1220 for maintenance operations ) .
Both
input 114 and
input 115 must
be high for
the FPLA to
operate .
When the FPLA detects the address for which new data
are to be supplied ( by its being included in the programmed
FPLA list ) , it asserts output lines FO through F7 and the
FLAG output . The low FLAG signal causes the output of
NAND - gate U1510A to be high . The U1510A high output
disables Address Line Buffer U1312 , which removes micro
processor
address bits
A3
through
A10
from the
buffered
address bus ; disables Device Address Decoder U1520 ,
which
removes the enable
signal from
the ROM that
had
been addressed ; and , through NOR - gate U1600A , enables
the Patch EPROM ( U1640 on Diagram 9 ) by supplying the
PATCH EPROM CS enable signal .
At the same time , FPLA outputs F0 through F7 are sup
plied to the address bus as address bits BA3 through BA10
respectively .
Because the Patch
EPROM is
enabled
, a
byte
in the ROM that is to be changed is replaced by a new byte
from the Patch EPROM .
Note that address bits , 1 , and 2 are not included in the
FPLA inputs and that these bits are not generated in the
FPLA output , which includes only bits 3 through 10. There
fore
, eight - byte
blocks are recognized
by the FPLA
. Each
address that is programmed into the FPLA corresponds to
an eight - byte block that is on an eight - byte boundary ( the
low - order ' three bits are Os ) . Thus , for any address , the low
er - order three address bits ( A0 through A2 ) are ignored by
the FPLA . A corresponding eight - byte block in the Patch
EEPROM is mapped in on top of the changed data . ( In ex
planation , note that address bits A0 , A1 , and A2 are applied
directly
through Address
Line
Buffer
U1320
and
so are ap
plied to the Patch EPROM regardless of whether the source
of the address is the Microprocessor [ Diagram 5 ] or the
FPLA . )
REV JUL
1982
Theory of
Operation - FG 5010
Further , note that on the function outputs of FPLA
U1420
( FO through
F7 ) , there are series
resistors
in
all lines .
The
purpose of these
resistors is
to
reduce
the
amount
of
current that flows during bus contention time . The propaga
tion
delay of the
LAG signal through gates U1510
and
U1312 can cause some bus contention . Resistors R1420
through R1427 limit the current that can flow during that
time .
Device Address Decoder
The
Device Address
Decoder
circuits
consist of decoder
U1520 and U1512 and associated logic gates . The circuits
generate
the
enable signals
for the
RAM
,
ROM ,
Address
Switch , GPIB Interface , Keyboard / Display Interface , Versa
tile
Interface
Adapter , and
Patch
EPROM from the
address
es
supplied on the
buffered bus
by
buffer
U1320 .
The U1520 decoder decodes eight kilobyte blocks . Out
put
YO
indicates
addresses
through IFFF ,
Y1 indicates
2000 through 3FFF , Y2 indicates 3000 through 4FFF , and
so
on
through FFFF .
Decoder U1520 is
supplied with only
address bits 13 , 14 , and 15. ( Output Y2 , Y3 , and Y4 are not
used . )
Of
the
output lines from
U1520
, the Y5 , Y6
, and Y7
lines
are used to enable the ROM's on Diagram 9. Output Y1 is
used to enable the Address Switch on Diagram 9. Output
YO is used for two purposes . It is used to generate the en
able signal for the GPIB Interface IC ( Diagram 7 ) , and it is
used
as one
of the
enabling
signals for the
bidirectional
buff
er
on
Diagram 7 .
The U1512 decoder decodes four two - kilobyte blocks in
each of two
eight - kilobyte
ranges .
This is
illustrated
in
Table
4-3 . Decoder U1512 is supplied with address bits 11 , 12 , 13 ,
14 , and 15. ( Outputs Y5 and Y6 are not used . )
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Table 4-3
ADDRESS DECODING
0- 7FF
800-
FFF
1000-17FF
1800-1FFF
8000-87FF
8800-8FFF
9000-97FF
9800-9FFF
Two
-
kilobyte
blocks
in
an
eight -
kilobyte range
Two -
kilobyte
blocks in
other
eight
-
kilobyte
range
an
Output Y7
of
U1512 , in
combination
with the
FLAG sig
nal from FPLA U1420 and through inverter U1730C and
4-51