Tektronix FG 5010

Theory of
Operation
- FG
5010
NOR - gate U1600A , enables the Patch EPROM ( Diagram 9 ) .
(
It is important
to
remember that
the Patch
EPROM can
be
addressed either by the
FPLA or by
addresses
in
the range
of
9800
through
9FFF
. )
Output Y4 is applied to the shift enable circuit which con
trols serial data on Loop 1. Along with the WR signal from
the Read /
Write
Control Logic (
Diagram 5 ) , the Y4
signal is
applied through NOR - gate U1600B to the shift enable flip
flop ( U1600C and U1600D ) . If both Y4 and WR are low at
the same time , the flip - flop is set . ( The flip - flop is set by a
write
operation in the address
range of 8000
through 87FF . )
It is reset by the Loop 1 strobe signal ( STROBE L1 ) from
the
Versatile
Interface
Adapter
U1720 (
Diagram
4 ) . The
SHIFT ENABLE signal is applied to the Loop 1 circuits to
allow
data
to be
shifted to
Loop
1 .
Thus , a write operation sets the flip - flop , which permits
data to be shifted to Loop 1. After the data have been shift
ed to Loop 1 , the process of strobing the data resets the
flip - flop so that no more data will be shifted into Loop 1 until
the flip - flop is set again . This reduces the amount of shift
clock
noise introduced
to
Loop 1 .
Output Y3 is
one of the two
decoder outputs
that en
ables
the
GPIB
Interface
circuits
(
Diagram 7 ) . A
second
en
able signal is required because decoder U1512 does not
include
ENABLE
in the
enabling
or
select
inputs , so the out
puts of U1512 become valid approximately 40 ns after the
addresses
become
stable
. This
is a
requirement for
ad
dressing
the
Versatile Interface Adapter U1720 (
Diagram 8 )
and is not
a
problem for the
Keyboard
/
Display
Interface
,
U1830 , also on Diagram 8 , or the RAM's ( U1400 and
U1500
) on
Diagram
7.
However
, it
would
present
a
problem
to the GPIB
Interface
U1102
(
Diagram
7 ) .
The IC used
for
U1102 requires that the addresses be stable for a short
period of time before the select signal is asserted . To pro
vide for this requirement , the YO signal from U1520 , which
does
include
ENABLE
in
the
inputs , is also
applied
to OR
gate
U1612C . Thus ,
Y3 from
U1512 provides the
specific
address and YO from U1520 provides the ENABLE
component .
Output Y2 enables the Keyboard / Display Interface IC
( Diagram 8 ) , output Y1 enables the Versatile Interface
Adapter IC ( also on Diagram 8 ) , and output YO enables the
RAM
circuits
on
Diagram 7
.
7
RAM / GPIB INTERFACE
Introduction
Processor Board Diagram 7 contains the RAM and GPIB
Interface
circuits
. In addition , this
contains
the
Bidirectional
Buffer and
various
gates
that exert
control over the
buffer
and
RAM
circuits .
4-52
The RAM circuits provide the required random access
storage
capacity
for FG
5010 operations
.
Two static
RAM
IC's are used to provide a total of 1 kilobyte of memory
capacity . The
GPIB
Interface
circuits provide the
communi
cations interface between the IEEE - 488 bus and the internal
FG 5010 data bus . Eight data bits and assorted command
and
reply
signals are
handled by
the
GPIB Interface
.
Additional circuits on the diagram are the Bidirectional
Buffer that
transfers
data
between
the
Microprocessor and
the associated bidirectional interface and data storage cir
cuits , and the logic circuits that affect buffer and RAM
operations .
For
ease of
understanding , the
Bidirectional Buffer
circuit
is described first .
Bidirectional Buffer
The Bidirectional Buffer U1200 transmits eight bits of
data in
either
direction while
providing
isolation
among
the
various circuits . Bidirectional input / output and storage de
vices , in addition to the Microprocessor , include the GPIB
Interface circuits , the Front Panel Interface circuits , the Ver
satile Interface Adapter circuits , and the RAM circuits .
Control for the direction of data transmission is provided
by the RD signal from the read / write control logic on Dia
gram 5. When the RD signal is low , data flow is from B to A
in the buffer , and data are being read into the micro
processor from
the
selected I / O circuit . When
the RD
line is
high , data flow is from A to B in the buffer , and data are
being supplied by the microprocessor to an I / O or storage
circuit
.
The enable signal applied to U1200 , pin 19 is generated
from a combination of the RD , FI and SELO signals by
gates U1722A and U1510C . The FI signal from the Forced
Instruction
/
Normal
jumper
on
Diagram
5 ,
ordinarily
high ,
is
applied to AND - gate U1722A along with the BA10 ( bus ad
dress 10 ) signal from the Address Buffer circuit on Diagram
6. The output from U1722A is applied to NAND - gate
U1510C along with the inverted ( by U1610A ) SELŐ signal
from
Device
Address
Decoder
U1520
on
Diagram
6 (
SELO is
the signal from the YO output line ) . Thus , as long as the
Forced Instruction / Normal jumper is in the Normal position
whenever bus address 10 is high , the U1722A output is
high . Whenever SELO then becomes low , indicating that the
address range is between and FFF , the second input to
U1510C is high and the low output enables U1200 . The net
effect is to
enable
data
transfer
only
when in
the upper half
of each two - kilobyte block in the address range of through
1FFF .
U
U
U
U
U
U
U