Tektronix FG 5010

n
C
C
C
n
n
Specifically
,
the
buffer is
disabled
for
the address
range
from
through
3FF ,
enabled
from 400
through
7FF , dis
abled
from
800
through
BFF
,
enabled
from
C00
through
FFF
,
disabled
from
1000
through
13FF
,
enabled
from
1400
through
17FF
,
disabled
from
1800 through
1BFF
,
and en
abled
from 1C00
through
1FFF
.
This
scheme
allows read
and
write
operations with
each of the
input
/
output
devices
without
the
possibility of bus
conflict
with the
Micro
processor during the times that it is reading from its internal
RAM
.
In
explanation of that possible
conflict ,
whenever
the
microprocessor is reading from its internal RAM , which is
assigned
addresses
through 7F , the
Microprocessor data
bus
lines
would
be
enabled for
a
write cycle
even
though
the
operation in progress is a read cycle . This would cause data
bus
contention
between the
Microprocessor
and
the
Bidirectional
Buffer .
Signal
BA10
, by
being
included
in
the
buffer
enabling logic ,
prevents
such
contention
.
Random
Access
Memory
The
RAM
consists of
IC's
U1400 and
U1500
,
with the
contents
of
the two
arranged
so
that each
contains four bits
of the eight
- bit data
bus word .
Bits 2 , 4 , 6
and 7 are
in
U1400 ; bits ,
1 , 3 and 5 are
in U1500 .
Data
transfer
to
and
from the RAM is
through the
bidirectional buffer U1200 .
Selection of
the
RAM for
either
a
read
or
write
operation
is
controlled
by the
RAM
Chip Select (
RAM
CS )
signal
from
Device
Address
Decoder
U1512 on
Diagram 6.
This signal is
inverted by
inverter
U1610F and
applied to
NAND
-
gate
U1510D along with the
BA10
signal
. From
U1510D
, the
out
put signal is
applied to each RAM
CS input ( pin 8 ) .
Thus , the
RAM IC's
can be
addressed
only
when bus
address
line
10
is high . This prevents an image of the RAM from falling be
tween
addresses and 3FF ,
which would then
cause
it to
be
written into in
parallel with
the
microprocessor
internal
RAM .
Data
direction
control
is
provided by the
WR
signal from
the read / write control logic on Diagram 5. When the WR
signal is low , data are written into the RAM ; when WR is
high , data are
read from
the RAM . The
WR signal
ends
within
20
ns
after the end
of the
Microprocessor
ENABLE
signal so that the data will still be valid at the end of WR .
This prevents possible problems where delayed cutoff of the
ENABLE
signal
could
allow writing
erroneous
data .
GPIB
Interface
The GPIB
Interface
circuits
consist
of the
GPIB
Interface
( U1102 ) and two GPIB Drivers ; one for data U1110 , and
one for handshake and bus management lines U1100 . GPIB
Interface U1102 sends and
receives
data
over the IEEE -
488
data bus via
GPIB Driver
U1110 , and
communicates with
the Microprocessor , on Diagram 5 , via Bidirectional Buffer
Theory of Operation - FG 5010
U1200
.
Data
transfer is
under
the
control of
commands
from the
IEEE -
488 bus
and
control
signals
from
various cir
cuits within
the FG 5010 .
GPIB
Interface
U1102 is
addressable
from
1800
through
1FFF
,
but is
accessible
only from
1C00
through
1FFF
. ( A
read or
write operation in
the
range of
1800
through
1BFF
would cause
invalid data to
be written
into the
interface IC
because the
Bidirectional
Buffer
would
not
be
enabled . ) The
normal
address
for
the
interface IC is 1C00
through 1C07 .
Eight register
addresses
are
defined by the
three register
select
lines (
RS0
,
RS1
,
and
RS2
) .
GPIB Interface U1102 requires that the address lines be
stable
before enabling
.
Thus ,
enable
delay is
provided
by
a
combination of signals from Device Address Decoders
U1512 and
U1520 on
Diagram
6.
Decoder U1512
provides
a low Y3
enable signal
whenever the
address
is in
the
range
of 1800 through 1FFF . Decoder U1520 provides a low YO
output whenever the address is in the range of through
1FFF . However , one of the enable signals for U1520 is the
ENABLE signal from the
Microprocessor on
Diagram
5 .
Thus , the U1520 YO output cannot be low until ENABLE
occurs . Signals YO from U1520 and Y3 fro U1512 are ap
plied through OR - gate U1612C to produce the U1102 en
able signal ( 9914 CS ) . Thus , U1102 is selectable only during
the time that ENABLE is true , which allows the address to
stablize .
Data
transfer
on
the
output side of
U1102 are
directly to
GPIB
Driver U1110 .
These consist of
DI01
through
DI08 ,
which
are
on
U1102 pins 38 , 37 ,
36 , 35 , 34 ,
33 , 32 , and
31 ,
respectively . Data transfer connections on the internal side
of U1102 are directly to Bidirectional Buffer U1200 . These
consist of D0 through D7 , which are on U1102 pins 10
through 17 , respectively .
The
interface IC
receives its
clock
signal from the 4
MHz
Clock
circuit
on
Diagram 5.
U1102
does
not
require syn
chronization with
this clock
signal however ,
since
synchroni
zation is accomplished by the write enable signal ( WR ) from
the read / write
control logic
on
Diagram
5
and the chip
select
signal ( 9914 CS ) from the Device Address Decoders on Dia
gram 6. These signals are applied to U1102 , pin 4 and 3 ,
respectively . The read / write signal ( R / W ) from the read /
write control logic on Diagram 5 is connected to the U1102
DBIN input ( pin 5 ) to control the direction of data flow
through
U1102 .
The interrupt output from pin 9 of U1102 is applied di
rectly to the interrupt input of the Microprocessor on Dia
gram 5 ; the trigger output is applied to the Trigger Logic
circuits on
Diagram 8 .
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