Tektronix FG 5010

Theory
of
Operation
-
FG
5010
Connected between the interface IC ( U1102 ) and the
IEEE
- 488 bus
, the GPIB
Driver U1110 is
enabled
in two
states . The pull - up enable signal applied to pin 11 is sup
plied by
OR -
gate U1612D
. Inputs
to
U1612D are
the
atten
tion
( ATN )
and end
of instruction
( EOI )
commands
from the
IEEE - 488 bus through GPIB Driver U1100 . Thus , the only
time
the pull
- up
enable is low is when
ATN and
EOI are both
low at the same time , which occurs only during a parallel
poll
. Driver
U1110
operates open -
collector at that
time , and
operates tri
- state
at all
other
times
.
Connected in the same manner , GPIB Driver U1100 pro
vides communication for handshake and bus management
signals . These include SRQ , ATN , EOI , DAV , NRFD , NDAC ,
IFC and REN . The CONT signal from U1102 is continuously
high
,
configuring
U1100 as
a talker /
listener
rather than
a
controller . The effect of the continously high CONT signal is
to divert the ATN , REN and IFC lines toward U1102 and the
SRQ line out toward the IEEE - 488 bus . ( For a controller , the
conditions
would
be
opposite . )
8 > KEYBOARD / DISPLAY INTERFACE
PERIPHERAL INTERFACE PORT
Introduction
Processor Board Diagram 8 contains the Keyboard /
Display Interface , Peripheral Interface Port , and Trigger
Logic
circuits
.
The Keyboard / Display Interface circuits provide the seg
ment drive signals that are sent to the Display Driver Board
to control lighting of the display segments on the front pan
el , and also provide the signals that directly control the state
of the front panel TRIG'D , ERROR , and NOT ENTERED
indicators . The Versatile Interface Adapter circuits ; 1 ) ac
cept data from the Bidirectional Buffer , perform the transi
tion from parallel to serial data and provide that serial data
stream to other FG 5010 circuits ; 2 ) accept serial data from
those other FG 5010 circuits , perform the transition from
serial to parallel data , and provide those data to the
Microprocessor via
the
Bidirectional Buffer , 3 ) provide
the
strobe signals that load serial data into the registers on oth
er FG 5010 boards ; and 4 ) provide several control signals to
the Keyboard / Display Interface and Trigger Logic circuits .
Additional
circuits
on the
diagram
are
the
Trigger Logic
circuits that generate the trigger / gate signal for the Loop 2
circuits .
Keyboard
/
Display
Interface
The Keyboard / Display Interface circuits consist of two
segments : the
Interface IC
( U1830 ) , and
the indicator
con
trol
logic
.
4-54
Interface IC
. The
interface IC
accepts data
from and
sends data to the Bidirectional Buffer on Diagram 7 , accepts
data
from the
keyboard on
Diagram 2 , and
supplies signals
appropriate to
control the
front - panel
indicators
. In the
case
of
the
segmented
number
indicators ,
this is
done
via
the
Display Driver Board ( Diagram 3 ) .
Interface
U1830 is
addressable in the
range from
1000
through
17FF
, but
is
accessible only
in the
upper half
of that
range
( from
1400 through
17FF )
.
Address
line BA
from
the
Address Buffers on Diagram 6 is the only one used directly
by
the IC
; the
addresses
are
ordinarily
1400 and
1401. The
RD
and
WR
signals
from
the
Read /
Write Control
logic on
Diagram
5
are
both
used by
the IC
.
The select
sig
nal
for the IC
is the
8279-5CS signal
from
Device
Address
Decoder
U1512 on
Diagram
6 and does
not
include EN
ABLE . Clock for the interface IC is the enable output ( EN
ABLE ) from the Microprocessor on Diagram 5 .
Parallel data connections to and from U1830 are on pins
12 through 19 , which are data bits through 7 , respectively .
These data bits are supplied to and from Bidirectional Buffer
U1200
on
Diagram 7. Inputs
RLO
through
RL7
on pins 38 ,
39
, 1 , 2 , 5 , 6
, 7 , and 8
respectively ,
are return lines
from the
keyboard
circuits
on
Diagram 2.
Note
that
each of
these
lines is isolated by a 10 k resistor to reduce static
sensitivity
.
Outputs A0
through A3
( pins 27 ,
26 , 25 , and
24 ) and BO
through B3 ( pins 31 , 30 , 29 , and 28 ) are the display segment
control signals and are applied to the Display Board Seg
ment Driver circuits on Diagram 3. Indicator select lines SLO
through SL3 ( pins 35 , 34 , 33 , and 32 ) are also supplied as
outputs to those same circuits , as is the blank display signal
( BD , on pin 23 , inverted by U1630C ) . Inverting the BD signal
ensures that
the
display will be
off if the
Processor
Board
is
removed
.
Indicator
Control Logic .
Integrated Circuit
U1830 out
puts
SLO , SL1
, and BD are
also used
to partly
control the
logic
circuits that
determine the
states of the
TRIG'D ,
ER
ROR and NOT ENTERED front panel indicators shown on
Diagram 2. The control exerted by these signals is to pro
vide the
blinking
state .
NOTE
The TRIG'D_front - panel indicator operates in three
states : on , blinking , and off . When the trigger input is
above the threshold ( positive slope ) the indicator is
on ; when the input is below the threshold ( positive
slope ) , the indicator is off ; when the input is making
the transition , the indicator blinks . For negative slope ,
the indicator is on when the trigger input is below the
threshold and off when the input is above the thresh
old . The ERROR and NOT ENTERED indicators both
blink when on conditions are met , but are never on
continuously .
( @ )
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