Tektronix FG 5010

n
C
n
П
П
П
П
C
Signals
SLO
,
SL1 ,
and BD
are
applied
to
NAND -
gate
U1620B
,
which
supplies
the
clock input to
counter
U1732
.
Note
that there is
an rc
filter
(
R1731
and
C1731
)
on
this
counter input line .
The
purpose of this
filter is to
eliminate
the
effects of the
positive
-
going
glitch
that
exists on the BD
output
of
U1830
during
the
blanking time
between 80 and
100 ns
after the
start of the
blanking time
while the
U1830
internal
data are
changing .
Resistor
R1634
acts
as
a pull -
up
to ensure that
the clock
input to the
counter is within
specifications .
Counter
U1732
outputs Q5 , Q6
, and
Q7 are
applied
to
NAND
-
gates
U1730A and
U1730B to
provide
a
signal
duty
cycle of 5/8
at the
output of
U1730B for a
flashing cycle that
is
pleasant
to
the eye . From
U1730B , the
output is applied
to AND - gate U1722 along with the LOGIC RESET signal
from the
service
interconnect
connector (
J1220
) on
Diagram
5. ( This is done to ensure that the indicators will not light
during reset operations . ) The output from gate U1722B then
is the signal that , gated by other signals , supplies the blink
ing component to the display . This signal is supplied to
gates U1612B , U1812A , and U1812B .
The PA2
output from
Versatile Interface
Adapter
U1720 ,
inverted by
U1630D , is applied
as the second
input to OR
gate
U1612B . From
U1612B
, the
output
is
applied
along
with the
PA3
signal
( also
from
U1720 ) to
NAND
- gate
U1812D
, which
supplies
the
direct control for
the front - panel
TRIG'D
LED
indicator
shown on
Diagram 2.
This
arrange
ment provides that the inverted PA2 signal determines
whether
U1612B will pass a
blinking
or
a
constant ( high )
signal to U1812D . If PA2 is high , the low output of U1630D
will cause U1612B to pass the blinking signal to U1812D . If
PA2 is low , the high output of U1630D will force a constant
high output to
U1812D
. This
signal , either
blinking
or high
, is
then gated through U1812D by a high PA3 output from
U1720 . Thus , bit 3 of the U1720 A - register determines
whether
the
TRIG'D indicator will be on or
off , and bit 2
of
that
register
determines
whether it will blink
or light
steadily
if
it
is
on .
The PA1 output from U1720 , in combination with the out
put from U1722B , determines the state of the output of
NAND - gate U1812A , which controls the ERROR indicator .
If PA1 is high ,
the blinking
signal from U1722B
is gated to
the
indicator
.
If PA1 is low ,
the
indicator is off .
The PAO output from U1720 and the output from
U1722B control the output
of
U1812B
, and
thus the NOT
ENTERED
indicator in
the
same
manner .
Versatile
Interface
Adapter
Versatile Interface Adapter U1720 , enabled by the 6522
CS
signal from
Device
Address
Decoder
U1512
on
Diagram
Theory
of
Operation - FG 5010
6 and
clocked by the
ENABLE
signal from the
Micro
processor on Diagram 5 transforms the bus parallel data to
a
serial
data
stream
and
strobes the
data into the
Loop
1
,
Loop 2 , or Sine Shaper circuits of the FG 5010. Also , U1720
transforms the
serial
return from
Loop
2 to
parallel
data that
are sent to the Microprocessor via the Bidirectional Buffer
on Diagram 7 .
Data input and output for U1720 is the data through 7
lines
connected to pins
33 , 32 , 31 , 30
, 29 , 28 , 27 ,
and 26 ,
respectively . These pin connections send data to and re
ceive data from Bidirectional Buffer U1200 . Address selec
tion lines , 1
, and 2 from
the
Address
Buffers
on
Diagram
6
are
connected to
pins 38 ,
37 , and
36 ,
respectively .
For
prop
er timing , the fourth address line A3 , is supplied unbuffered
to pin 35
from the
Microprocessor
on
Diagram
5 .
Strobe and control outputs from U1720 include the PAO
through PA7 and PB0 through PB7 signals . As described
previously , the PAO , PA1 , PA2 , and PA3 signals are used in
the logic that controls the front - panel indicators . The PA4 ,
PA5 , and PA6 signals will be discussed later in the Trigger
Logic description .
Output PA7 from U1720 drives the Mag Latch Strobe
Generator circuit ( on Diagram 4 ) and is called LATCH TRIG
GER . This trigger output must be held low by U1720 for the
duration
of the
mag latch strobe
output of the
strobe gener
ator . If
MAGLATCH
TRIGGER is allowed to
become high
before the strobe ends , the strobe will be terminated . For
that reason , the trigger is held until a return is received from
the strobe generator . The return is the END OF STROBE
signal to CA1
( pin 40
) of
U1720 .
Outputs PBO through PB5 are the strobe output lines to
the
various FG 5010
boards
. PBO
is the
Output Amplifier
strobe and is
called
STROBE
A ( see
Diagram
25 ) .
PB1 is
the Loop 1 strobe and is called STROBE L1 ( see Diagram
10 ) . PB2 and PB3 are the Loop 2 strobes and are called
STROBE 2L2 ( see Diagram 17 ) and STROBE 1L2 ( see Dia
gram
19 ) ,
respectively . PB4
is the Sine
Shaper
strobe and is
called STROBE SS ( see Diagram 20 ) . Each of these strobes
causes data that have been serially shifted to the respective
board to be loaded into latches on the board .
Output PB5 is the Loop 2 status strobe and is called
STROBE
L2
STATUS
( see
Diagram
19 ) . This
strobe causes
status data for Loop 2 to be loaded into the shift register on
the
Loop 2 Board
and then shifted
in serial form
to U1720 .
Signals CB2 , PB6 , and CB1 are used to control the
bidirectional transfer of serial data between the Versatile In
terface Adapter IC ( U1720 ) and the other circuits of the
FG 5010. Pin
19 , CB2 , is
the data
input and
output
connec
4-55