Tektronix FG 5010 User Manual

Theory of
Operation - FG
5010
tion . The direction of data transfer is controlled by the PB6
signal and the shift register control bits in the Auxiliary Con
trol
Register
of
U1720 .
When PB6 is high , tri - state buffer U1232B is disabled
and CB2 is set ( in U1720 ) as an output to shift data out . The
output data stream is buffered by AND - gate U1722C , which
includes a pull - up
resistor on its
output
(
R1902
) to
ensure
the proper logic levels . The SHIFT CLOCK output comes
from CB1 , which is inverted twice by U1800A and U1610D .
Inverter
U1600D
serves as the
output
buffer
.
When PB6 is
low , tri - state
buffer
U1232B
is
enabled
and
CB2 is set ( in U1720 ) as an input to receive serial data from
Loop 2.
Data from
Loop 2 (
Diagram
19 )
are
inverted by
U1610E , then applied to the D input of flip - flop U1810A . The
flip - flop ,
clocked by the
inverted
U1720 CB1
output ,
delays
the input
data by half a
clock cycle .
From
U1810A , the Q
output is applied through tri - state buffer U1232B , which
again
inverts the
signal , to
U1720
input
CB2
.
The
reason for the half
- clock - cycle
delay is
that
U1720
shifts data in on
the
positive -
going
clock edge
.
However , the
shift
registers also shift
data
on
the
positive
-
going edge
.
Thus ,
dependent upon set -
up times and
internal delay
times
,
U1720
may
or may not
accept
the
first
input data bit .
To
prevent loss
of the
first bit ,
each data bit is
delayed
one
half clock cycle
by
U1810A
.
The CB1 shift
clock is
inverted
U1800A and
applied to the
clock
input of
U1810A
,
which
latches
data
on the rising
clock edge .
The
inversion in
U1800A
causes
U1810A to
latch
the
data bit
present at
the
D input on the negative transition of CB1 and hold that data
until the
next
negative
transition . This
causes
the
data at
CB2
to
remain
stable
during
the
positive
transition of CB1 ,
preventing
data
loss .
Trigger
Logic
The
Trigger Logic , under
control
of
signals from the
Ver
satile
Interface
Adapter
U1720
,
produces
the
TRIG
/
GATE
OUT
signal
that is
supplied to the
Loop
2
Trigger
/
Gate Input
Amplifier
circuit
on
Diagram
15.
Outputs PA4 , PA5 ,
PA6 ,
and CA2
from
U1720 provide the
control
.
PA4 is
applied
to
the D input to
flip - flop
U1810B
. If
enabled
by PA5 and
the
TRIG
input from
GPIB
Interface
U1102 on
Diagram 7 ,
CA2
from
U1720 clocks the flip -
flop . ( In
U1800D
,
PA5
deter
mines
whether or not
the
TRIG
input
signal
will
be
allowed
to gate
the CA2
clock
through gate
U1800C
to
flip - flop
U1810B . )
Output
PA6 from
U1720
controls
whether a
trigger
signal
or a gate signal will be supplied to Loop 2. If PA6 is high ,
flip - flop
U1810B is
held
reset
.
The Q
output
is
thus
high
and
the
signal from
U1800C
is
gated
through
U1800B
and
U1812C .
4-56
If U1720 output PA5 is low , the TRIG input from the
GPIB
Interface
IC on
Diagram
7
, which
pulses
high
on a
Group
Execute
Trigger
, is
disabled
. The
output
of
gate
U1800D is then high and a negative - going CA2 pulse will
cause a positive - going pulse at the U1800C output . This
positive - going pulse is then inverted twice , once by U1800B
and once by U1812C , and applied out to the Loop 2 trigger
circuit
.
Thus , if the
user
presses the
front - panel
trigger
switch
to
put the FG
5010
in
trigger
mode
, and
then
presses
the front -
panel
manual trigger switch ,
the
Microprocessor
will cause a negative - going pulse from CA2 , which will be
gated through U1800C , U1800B , and U1812C to become a
positive - going output trigger / gate pulse ( see Fig . 4-20 ) .
When the
DT TRIG
command is
received by the
FG 5010 , the
Microprocessor will cause
PA5 to be
set high .
This will enable
the TRIG output
from the GPIB
Interface
IC .
The TRIG output
becomes
high
when a Group
Execute Trig
ger is received and remains high during the time that the
Group
Execute Trigger
is
actually
present
on the
bus . Thus ,
from the
time that
data are
declared valid on a
Group
Ex
ecute
Trigger ,
plus
or
internal clock cycles for the GPIB
Interface IC ,
there will be a
signal present on the
TRIG
input
line .
If PA5 is
high , that
positive
-
going trigger
becomes
a
neg
ative - going trigger at the output of U1800D . With that low
from
U1800D and a high
CA2 output
from U1720
, the
U1800C output will be high . The signal will be inverted
twice , once by
U1800B and
once by U1812C ,
and applied
out as a positive - going trigger / gate pulse to the Loop 2 trig
ger circuit ( see Fig . 4-21 ) .
When
a
gate is
required rather than a
trigger
, the
PA6
U1720 output
is set low .
This
removes the reset from
flip
flop U1810B and cause a high output from U1800B . The
high output from U1800B applies a high input to U1812C ,
which then
acts as an
inverter
for
whatever signal is at the
Qoutput of flip - flop U1810B .
When a manual gate is required , PA5 is set low . With
PA5 low , the output of U1800D is high and CA2 is inverted
by U1800C .
Setting PA4 high
and clocking flip -
flop U1810B
by pulsing CA2 low causes the high on PA4 to be loaded
into the flip - flop . The flip - flop Q output is thus driven low ,
inverted by
U1812C , and a
high is
supplied
to
the Loop 2
trigger
circuit
.
That
high remains
until PA4
is
changed to a
low and CA2 is pulsed low again . That low is clocked into
the flip - flop , placing a high at the Q output , which is inverted
by
U1812C and
becomes a
low at the
trigger /
gate
output
to
Loop 2. (
see
Fig.4-22 ) .
When the
DT GATE
command is
received by the
FG 5010 ,
output PA5 from
U1720 is set
high . When this
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Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English