Tektronix FG 5010 User Manual

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C
C
C
17
TRIG
(
@
)
17
PART
OF
U1720
PB7
PA4
CA2
PB7
PAS
PA6
PART OF
U1720
CA2
6 X
39
v
B.
7 L
12
8
H
X
2/3
39
13
A.
DETAILED
DIAGRAM .
( X =
DON'T
CARE
)
u
11
8
U18000
8
9
U1800C
10
U1800C
J
SIMPLIFIED
SIGNAL
PATH .
6
10 11
occurs , a TRIG pulse from the GPIB Interface IC will cause
the
output of
U1800D to
become low ( TRIG is
active high
) .
This TRIG pulse
is
generated during the time
that data valid
is true
on the
Group Execute
Trigger
multiline
signal . ( The
leading edge of the signal becomes high between 1 and
1 1/4 μs
after
data valid ; that is
, 4 to 5
clock
cycles
after
data
valid
is
asserted
on
the
Group
Execute
Trigger
byte . )
When
TRIG becomes high ,
the Q
output
of
U1810B
be
comes
low (
the
U1720 CA2
output will be in its
normal high
state ) , and
the
output of
U1800C will
become high . The
positive - going clock edge will have clocked flip - flop U1810B .
In
this
manner ,
when
the Group
Execute
Trigger
occurs , it
will
cause the
trigger
/
gate output to
Loop
2 to be
high . (
see
Fig
. 4-23 ) .
The Microprocessor will then determine what caused the
Group Execute Trigger interrupt , and set PA4 back to the
low state .
Thus , the
next time
that the
Group Execute Trig
ger is received , the output gate will be turned off ( low ) .
U1800B
10
Н
H
U1810B
R
6
5
V
Q
12
H
10
9
U1800B
9 8
Theory of Operation - FG 5010
U1812C
U1812C
P1050-58
n
8
Fig .
4-20 .
Generation of
trigger
from front
panel
(
MTRIG
command
)
.
HP
TRIG
/
GATE
OUT
(
LOOP2
)
J1050
3467-40
The output gate can be toggled by consecutive Group
Execute
Triggers
since
,
each time
the
Microprocessor re
ceives
a
Group
Execute
Trigger
, it
examines the
signal that
is fed back
as PB7
to
determine
whether or not
the PA4
signal was accepted . If it was , the output is set to turn the
gate on ( or off ) , and the PA4 signal is inverted . Thus , the
hardware actually causes the FG 5010 output to be turned
on or off
with
timing that
varies
approximately 1 μs
from the
timing of the Group Execute Trigger on the bus , while the
software
is
still in
control
of
actual
operation
.
( 9 ) ROM / ADDRESS SWITCH
Introduction
Processor Board ( Diagram 9 ) contains the ROM and De
vice
Address
circuits
, plus
the bus buffers
for both of
these
circuits , and the power connections for the board .
4-57

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English