Tektronix FG 5010 User Manual

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burst , or triggered modes are selected . The diode is driven
by
the
Clamp Voltage
Generator
.
The Shrink Control Amplifier is controlled by the loop
capacitor selection relays , and the ramp rate control
voltages , Vup and VDN . Depending on the capacitance
selected
and
the ramp
rates of the
triangle
wave , the
shrink
control circuits feed more or less current to the Level
Detector to compensate for loop delay . The +10 V
reference is also fed to the shrink control circuit .
Input
triggers from the slope
level
selection circuit in
Loop 2 and
the end - of -
burst signal from
the sine
shaper is
applied to the Trig / Gate / Burst Logic circuit . The square
wave from the HF Square - wave Buffer is also applied to this
circuit . The output of the Trig / Gate / Burst Logic circuit is
applied to the Clamp Enable Switch to enable and disable
the phase clamp circuit , as required . The logic circuit also
sends a signal to the Loop 2 circuits to indicate when clamp
enabling
has occured
.
The DAC circuits receive the +10 V reference and
control from the CPU by way of a latch . The output and the
+10 V
reference
are fed
to the Clamp
Phase
Voltage
Generator and the Lock Phase Voltage Generator . The
output of the Clamp Phase Voltage Generator is a voltage
that is approximately equal to the Trig / Gate / Burst baseline
voltage .
The output of the Lock Phase Generator is a voltage
that is used by the Loop 2 circuits to determine the phase
difference
between the
input
and
the
output
signals
during
phase -
lock
operation
.
DIGITAL CONTROL CIRCUITS
The Digital Control Circuits
are
the
means
of
communication between the CPU and the Loop Circuits . As
the operator , user , or Controller requires another setup to
be made by the FG 5010 , the CPU sends an instruction
word to each
segment
of the FG
5010 ,
including the Loop 1
circuits . The Loop 1 digital control circuits consist of latches
U1602
,
U1701 , U1702
and buffer
U1012 (
Diagram
10 ) ;
U1501 , U1502 , and U1601 ( Diagram 11 ) ; U1301 and U1401
( Diagram 13 ) ; and U1141 ( Diagram 14 ) . Refer to Diagram
10. The
STROBE
L1 ,
SHIFT ENABLE ,
SHIFT
CLOCK
, and
SERIAL
DATA
IN signals
enter the board
and are applied
to
Buffer U1012 , which converts the TTL levels needed to
operate with
the
CMOS
latches .
@
Theory of
Operation -
FG 5010
All nine latches are connected in series to form a 72 - bit
shift
register
.
Following the
positive
excursion of the SHIFT
ENABLE signal from the CPU , U1012B and C enable both
the CLOCK signal from U1012 pin 10 and the DATA signal
from U1012 pin 2 to pass to the Register . The data are
shifted through the register until the entire 72 - bit group is
loaded . SHIFT ENABLE then returns low to keep the
CLOCK
and
DATA lines
quiet when
shifting
is
not
occurring .
Following the
loading
cycle
, the
STROBE signal , which
is
applied to each eight - bit register , transfers the data from the
serial register elements to the register output lines , and the
Loop 1 Circuits are presented new instructions .
10
LOOP 1 REFERENCE CIRCUITS
Introduction
Refer to Fig . 4-3 , which is a simplified diagram of the
Loop 1 Reference Circuits . The principal circuits depicted on
Diagram 10 are the Frequency Reference Selector , the
+10 V Reference , the DAC Reference Amplifier , and the
Frequency
DAC
.
TheLock Freq control voltage signal enters the circuit
and is applied to ø LOCK transmission gate U1821B , and is
applied as one of the summing inputs to summing amplifier
U1831 . The FM / VCF input passes through buffer U1731B ,
where the signal either passes through VCF transmission
gate U1821A to be the second summing input to U1831 , or
the FM voltage from the buffer passes through U1821C to
be summed with the +10 V reference at the input of
U1731C , the DAC Reference Amplifier . The summed volt
age is applied to the reference input of the Frequency DAC ,
modified by the digital information from the CPU , then
processed and passed to U1831 as the third summing input
to that amplifier . The resulting output of the reference cir
cuits is a dc voltage that is proportional to the sum of the
values
fed
into the
output
summing
amplifier
.
+ 10 V Reference
This circuit consists of amplifier U1731A , Zener diode
VR1831
, and
related
components . The
noninverting
input
of
U1731A is controlled by divider R1736 - R1833 , which is con
trolled by the voltage across VR1831 . The output of the
amplifier is controlled by adjusting R1735 , the 10 V Adj po
tentiometer . The output , a precise +10 V , is combined with
the output of analog transmission gate U1821C , then ap
plied to the DAC Reference Amplifier , discussed later in this
description . The +10 V reference is applied elsewhere in
Loop 1
.
4-7

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English